Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-05-09
2006-05-09
Lee, Thomas C. (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C711S167000
Reexamination Certificate
active
07043657
ABSTRACT:
A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.
REFERENCES:
patent: 5361277 (1994-11-01), Grover
patent: 5422918 (1995-06-01), Vartti et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5528187 (1996-06-01), Sato et al.
patent: 5696951 (1997-12-01), Miller
patent: 5734685 (1998-03-01), Bedell et al.
patent: 5896055 (1999-04-01), Toyonaga et al.
patent: 5909473 (1999-06-01), Aoki et al.
patent: 5926837 (1999-07-01), Watanabe et al.
patent: 5987576 (1999-11-01), Johnson et al.
patent: 6111448 (2000-08-01), Shibayama
patent: 6330627 (2001-12-01), Toda
patent: 6426984 (2002-07-01), Perino et al.
patent: 6563358 (2003-05-01), Goulette
patent: 6745271 (2004-06-01), Toda
patent: 6771107 (2004-08-01), Saeki
Chang Shuen-Chin
Kim Young Gon
Park Yong E.
Tung Chiayao S.
Yang Jeongsik
Integrated Memory Logic, Inc.
Lee Thomas C.
Sidley Austin LLP
Wang Albert
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