Universal structure for memory cell characterization

Details Universal structure for memory cell characterization Universal structure for memory cell characterization

2011-05-03

2011-05-03

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S154000, C365S156000

Reexamination Certificate

active

07936623

ABSTRACT:
An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a first storage node set, a second storage node set, and a set of other nodes, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type and are not connected together, where each node in the first storage node set is connected to a port in the first port set, where each node in the second storage node set is connected to a port in the second port set, where each of the other nodes is connected to one of the other ports, and where each of the other ports is connected to one and only one of the other nodes.

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U.S. Appl. No. 11/945,469, filed Nov. 27, 2007, Deng, Entire Document.

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