Universal single-ended parallel bus

Details Universal single-ended parallel bus Universal single-ended parallel bus

2007-12-25

2007-12-25

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S090000, C326S126000

Reexamination Certificate

active

11591406

ABSTRACT:
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.

REFERENCES:
patent: 5512853 (1996-04-01), Ueno et al.
patent: 6124177 (2000-09-01), Lin et al.
patent: 6184717 (2001-02-01), Crick
patent: WO 81/01780 (1981-06-01), None

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