Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-11-12
2001-04-17
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S014000, C710S052000, C710S100000, C710S120000, C709S226000, C709S250000, C370S259000, C370S420000, C370S524000
Reexamination Certificate
active
06219736
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of general purpose microcomputers and particularly to a microcomputer unit including a serial interface controller such as the Universal Serial Bus (USB) RAM device to facilitate communication between a host and a microcontroller.
2. Description of the Prior Art
The growth of desktop computers has been accompanied by a corresponding growth in the number and types of peripheral devices that have various connection/interconnection schemes, etc. Accordingly, today's PC's have many peripheral connectors, most of which are expensive. As the size and cost of the PC decreases, the relative cost of these connectors increase. To alleviate this problem, high performance serial bus schemes are being defined that are designed to use one connector to attach many (lower performance) peripherals to the PC. Furthermore, due to the operational limitations of many of these peripheral devices with respect to what is referred to in the computer industry as “low speed”, they typically require dedicated wires and connectors capable of supporting much higher speed data transfers than are required.
Moreover, information flows and the required responses over a high performance serial bus exceed the performance capability of generic microcontrollers of the type used in typical peripherals.
The Universal Serial Bus (USB) and “firewire” (IEEE 1394) has been introduced in the computer industry to effectuate “time sharing” of many of these low speed peripheral devices over a single higher speed connection thereby providing higher performance communication links while using such peripheral devices. This higher speed connection requires only minimal resources (such as I/O, DMA, Interrupt and Memory) from the host system. Prior art systems require such resources per peripheral.
By way of background, a summary of the USB and its operation is presented below. Although the preferred implementation of the serial interface bus is the USB, a similar approach will work with the faster “firewire” (IEEE 1394) operating at 100,200,400 . . . Mbits/sec.
DESCRIPTION OF THE UNIVERSAL SERIAL BUS
The characteristics of a USB communication link consists of a half duplex 12 Mbit/sec channel divided into 1.0000 millisecond “frames”, which are distributed over a Tiered Star Topology.
FIG. 1
shows an example of a system using USB to communicate to a host (not shown). In
FIG. 1
, a USB host controller unit
100
is shown coupled to a PCI bus
102
for communicating information through the PCI bus to other peripheral devices, or hubs, that may be coupled to yet further peripheral devices. In
FIG. 1
, the peripheral devices: phone device
104
, a monitor device
106
and another hub device
108
are coupled through ports to the USB host controller device
100
. The monitor device
106
is further coupled to a plurality of other peripheral devices, such as two speaker units
110
and
112
, a microphone device
114
and a keyboard
116
. The keyboard
116
is further coupled to a mouse device
118
and a pen device
120
through ports.
All USB devices attach via a USB hub providing one or more ports. While each hub can provide either a high speed (12 Mb/s) or low speed (1.5 Mb/s) device support, only the high speed version will be considered for simplicity. Connectors and line characteristics are described in the USB Specifications, and are herein incorporated by reference. In the interest of maximum compatibility, Intel and the USB Implementors Forum make available a VHDL description of the Serial Interface Engine (SIE). A line driver (such as Phillips USB translation PDI-USB-P11) uses differential pair signaling with bit-stuffed NRZI (Non-Return-to-Zero, Inverted) coding.
Every transfer across a USB interface consists of a combination of packets. Four classes of transfers have been defined, each of which provides features useful to typical peripheral devices. Eeach transfer class will be described briefly:
Interrupt Transfer
Useful for devices that typically interrupt the host system in non-USB interface. USB interrupt transfers provide a maximum latency on the order of one millisecond, with average latency perhaps half that.
Control Transfer
Useful for sending specific requests from the host system to USB devices. This transfer is typically used during device initialization.
Bulk Transfer
Useful for data transfers that have no immediacy or periodicity requirements, such as the data returned from a floppy disk device.
Isochronous Transfer
Useful for periodic transfers or for devices requiring a constant data rate, such as voice communications over an ISDN phone.
A transfer class is typically associated with a device endpoint. The user of a USB device must analyze the transfer class(s) necessary for his purposes, and define appropriate endpoints. The endpoints are communicated to the USB host controller during the configuration process, using descriptors, which are data structures with a defined format. Each descriptor begins with a byte-wide field that contains the total number of bytes in the descriptor followed by a bytewide field that identifies the descriptor type. For endpoint descriptors, at least the following fields are required: Descriptor Length, Descriptor Endpoint Type, Endpoint address, and Endpoint attributes. An example of a device descriptor and the descriptor communications procedure is given in a following section.
The connection between client software on the host system and an endpoint on a peripheral device is via a Pipe. Typically a pipe connects the client data buffer on the host with an endpoint register on the device. The client software initiates a control transfer to read the device's descriptor(s), then registers the required endpoints with the system's USB host controller, which allocates USB bandwidth according to an implementation specific plan.
USB bandwidth allocation is highly flexible and device specific. Interrupt pipes can specify a latency ranging from one to 255 msec. An endpoint can define a maximum packet size, thereby allowing the host controller/allocator to compute the number of specific endpoints that can share a frame. Maximum packet size can be up to 64 for Interrupt endpoints, but as large as 1023 for Isochronous endpoints.
USB devices are not required to have a specific number or type of endpoint(s). The specific configuration for each device is set up during initialization. Since all SETUP and associated packets are CONTROL transfers, then at a minimum, any device must have at least one control endpoint. The USB-RAM interface described herein will support CONTROL, INTERRUPT, ISOCHRONOUS, and BULK transfers, as required by the microcomputer being interfaced to the USB-RAM.
CONTROL transfers begin with a setup stage containing an eight byte data packet, the eight bytes defining the type and amount of data to be transferred during the data stage. CONTROL transfers are guaranteed at least 10% bus allocation. In order to apportion control transfers over as many devices as possible, the data stage of a CONTROL transfer is limited to 64 bytes. Typical USB transactions consist of three phases:
Token
Data Packet
Handshake
Phase
Phase
Packet Phase
All USB transactions begin with a token phase, defining the type of transaction to be broadcast over the USB. The four USB tokens are:
SOF (Start_of_Frame) begins each 1 ms frame
SETUP begins each CONTROL transfer
IN begins a data transfer from the device to the host
OUT begins a transaction to transfer data from the host to the device.
SOF and SETUP tokens are very specific, while IN tokens can be used in INTERRUPT transfers, BULK transfers, ISOCHRONOUS transfers, and the data phase of CONTROL transfers. The Token phase is always from the host to the device. The Data Packet direction varies according to the transaction, and the Handshake, if required, usually depends on the data direction. Each of the above packet phases transfers a packet with the following format:
[SYNC Seq.][Packet ID][Packet Info&r
Hamrick Claude A. S.
Lee Thomas C.
Oppenheimer Wolff & Donnelly LLP
Peyton Tammara
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