Universal serial bus interfacing using FIFO buffers

Details Universal serial bus interfacing using FIFO buffers Universal serial bus interfacing using FIFO buffers

2000-04-07

2004-06-29

Lefkowitz, Sumati (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S106000, C710S305000, C710S306000

Reexamination Certificate

active

06757763

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bus interfaces, and in particular, to a system and method for interfacing a Universal Serial Bus controller (UDC) which is connected to the USB and an XBUS.
2. Description of the Related Art
The Universal Serial Bus (USB) is a bi-directional, isochronous, dynamically attachable serial interface providing two wire point to point signaling. Signals are differentially driven at a bit rate of 12 megabits per second.
Typically, a USB host controller is incorporated into a bus bridge which couples the USB to a peripheral bus. Such a peripheral bus typically runs at a different clock than the USB. As such, there is a need to synchronize the USB data with the peripheral bus data.
While the Universal Serial Bus is intended as an industry-wide standard peripheral interface, the USB Specification does not define the relationship between components in USB devices or in computer systems employing the USB.
SUMMARY OF THE INVENTION
These and other drawbacks in the prior art are overcome in large part by a Universal Serial Bus interface according to the present invention. Briefly, an improved Universal Serial Bus interface employing FIFO buffers for interfacing to the application bus of the UDC and an XBUS is provided. The interface includes a plurality of transmit/receive channels multiplexed to the USB and the XBUS.
Each transmit channel includes a transmit FIFO buffer, a transmit write buffer, a transmit push buffer, and three transmit state machines: a transmit write state machine, a transmit interrupt state machine, and a transmit push state machine. The transmit state machine and the transmit FIFO are clocked in the USB domain. The transmit write register is clocked in the XBUS domain. Each receive channel includes a receive FIFO buffer, a receive state machine, and a receive register. The receive FIFO, the receive state machine, and the receive register are all clocked in the USB domain.


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