Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2000-09-19
2002-03-26
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S832000, C257S685000, C257S686000
Reexamination Certificate
active
06360433
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip modules, and more particularly to a chip module including a highly configurable chip array which is interconnectable to a universal package capable of hermetically sealing the chip array.
There is currently known in the prior art chip modules comprising a chip array which is mounted into a package for purposes of protecting the chip array from contaminants such as dust and moisture. The package may also be used to convert the chip array to a particular standard pin format. The chip array typically comprises a substrate (e.g., a circuit board) having off-the-shelf, pre-packaged memory or logic devices (e.g., TSOP packaged chips) mounted to one or both of the opposed sides or faces thereof. This chip array is mounted into and sealed within the associated package of the chip module. These prior art chip modules wherein the chip array is sealed within the package to protect the same from contaminants are often used to achieve compliance with stringent military standards such as the JET “X” standard which require extremely low susceptibility to component failure as a result of contamination from external or environmental sources.
Though prior art chip modules are generally suitable for protecting the chip array within the associated package from external contamination, they possess numerous deficiencies which detract from their overall utility. One such deficiency lies in the inability to test the currently known chip modules until the completion of the package assembly process. Due to the complexity of their construction which is attributable in large part to the heat and moisture sensitivity of the internal chip array, such chip modules experience a relatively high failure rate during initial testing. Another deficiency lies in the inability to recover components from these chip modules in the event the same are unsuccessfully tested. For example, if the failure of the chip module during testing is attributable to a soldering problem, the chip module must be scrapped in its entirety due to the currently known configurations and assembly methods related thereto not allowing for the recovery or salvage of either the chip array or the package.
A further deficiency of the prior art chip modules is that the package thereof is device specific, i.e., tailored to accommodate a particular chip array. As such, since the chip array is not confined to one specific configuration but may have any one of a multitude of differing configurations, any particular chip array will typically require a different device specific package. In this respect, the development of a new chip array carries with it the need to develop a new package, and hence new tooling as well as a new assembly protocol. As will be recognized, these constantly changing tooling and assembly requirements significantly increase the product costs of prior art chip modules. Moreover, the configuration of such prior art chip modules, and in particular the chip arrays thereof, does not lend itself to use with newly developed memory or logic devices, thus increasing susceptibility to obsolescence.
The present invention addresses and overcomes these deficiencies of prior art chip modules by providing a low cost, high reliability, high density chip module wherein a highly configurable, custom chip array is interconnectable to a “universal” package. In the present chip module, the chip array includes a novel and unique interconnect substrate having an interconnect array which is specifically adapted to electrically communicate with a corresponding interconnect array provided within a cavity of the package. In view of the complementary nature of these interconnect arrays, the package is universal in the sense that it may be used in conjunction with any chip array including the interconnect substrate. The package in the present chip module, in addition to being usable with any chip array including the interconnect substrate, is adapted to convert such chip array to a standard sixty-eight (68) pin format.
In addition to providing economies in the manufacturing/assembly process and thereby significantly reducing product cost, the configuration of the present chip module and assembly methodology preferably employed in relation thereto allows for the testing of the chip array prior to the mounting of the same within the package, and the testing of the combined chip array/package prior to the chip array being sealed within the package. As a result, in the present chip module, either the chip array or the package may usually be salvaged in the event of an unsuccessful result being obtained during the testing process. Moreover, the configuration of the chip array of the present chip module provides a high level of adaptability to new memory or logic devices, thus substantially eliminating its susceptibility to rapid obsolescence. The completed chip module formed in accordance with the present invention also satisfies the most stringent military standards. These, and other advantages attributable to the present invention, will be described in more detail below.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a chip module which includes a universal package for accommodating any one of uniquely configured chip arrays (e.g., memory or logic arrays). In the preferred embodiment, the chip array, which is a sub-assembly of the chip module, comprises an interconnect substrate having opposed, generally planar surfaces and including a first interconnect pad array disposed on at least one of the surfaces thereof. The interconnect substrate preferably has a generally square configuration defining four peripheral edge segments, with the first interconnect pad array extending along one of the peripheral edge segments. The first interconnect pad array itself preferably comprises first and second sets of conductive interconnect pads which are disposed on respective ones of the opposed surfaces of the interconnect substrate and extend along a common peripheral edge segment thereof. The conductive interconnect pads of the first and second sets are arranged in identical patterns such that the conductive interconnect pads of the first set are aligned with respective ones of the conductive interconnect pads of the second set. Additionally, a plurality of vias are preferably extended through the interconnect substrate between respective pairs of the conductive interconnect pads of the first and second sets thus establishing electrical contact or communication between the pads of each pair.
In addition to the interconnect substrate, the chip array of the present chip module comprises at least one integrated circuit chip which is attached to the interconnect substrate and electrically connected to the first interconnect pad array. In the present chip module, the integrated circuit chip is preferably incorporated into a packaged chip having a plurality of chip leads protruding therefrom. The chip leads are electrically connected to respective ones of a plurality of conductive lead pads which are disposed on at least one of the opposed surfaces of the interconnect substrate and are electrically connected to the first interconnect pad array. It is contemplated that the interconnect substrate of the chip array may include a plurality of conductive lead pads disposed on respective ones of the opposed surfaces thereof, with the chip leads of at least two packaged chips being electrically connected to the conductive lead pads on respective ones of the opposed surfaces of the interconnect substrate. As indicated above, the chip array may comprise a memory array or a logic array, with each of the packaged chips preferably being a memory or logic device selected from the group consisting of a TSOP I package, a TSOP II package, a QFP package, and a CSP package or the like.
Though the interconnect substrate of the chip array of the prese
Arbes Carl J.
Stetina Brunda Garred & Brucker
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