Universal memory circuit architecture supporting multiple...

Details Universal memory circuit architecture supporting multiple... Universal memory circuit architecture supporting multiple...

2008-07-29

2008-07-29

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S107000, C711S202000

Reexamination Certificate

active

07406572

ABSTRACT:
An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured for accessing a different type of memory array other than the MRAM array. A smart MRAM interface block is also included and coupled between the plurality of memory interface blocks and the MRAM array. The smart MRAM array is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array. A method for operating the improved non-volatile memory device is also disclosed herein.

REFERENCES:
patent: 5640536 (1997-06-01), King et al.
patent: 5928347 (1999-07-01), Jones
patent: 6047361 (2000-04-01), Ingenio et al.
patent: 6404671 (2002-06-01), Reohr et al.
patent: 6434660 (2002-08-01), Lambert et al.
patent: 6795906 (2004-09-01), Matsuda
patent: 2002/0095280 (2002-07-01), Tung et al.
patent: 2002/0147882 (2002-10-01), Pua et al.
patent: 2003/0041203 (2003-02-01), Jones et al.
patent: 2003/0043624 (2003-03-01), Roohparvar et al.
patent: 2003/0067814 (2003-04-01), Piau et al.
patent: 2004/0117688 (2004-06-01), Vainsencher et al.
patent: 2004/0143693 (2004-07-01), Hwang
patent: 2004/0168015 (2004-08-01), Roohparvar et al.
patent: 2004/0193782 (2004-09-01), Bordui
patent: 2005/0060464 (2005-03-01), Alva et al.
patent: 2005/0060465 (2005-03-01), Wyatt et al.
U.S. Appl. No. 10/927,980 entitled “Universal Memory Architecture with MRAM,” filed Aug. 27, 2004.

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