Universal logic level shifting circuit and method

Details Universal logic level shifting circuit and method Universal logic level shifting circuit and method

1997-12-08

1999-04-20

Tokar, Michael

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 81, 326 68, H03K 190175

Patent

active

058960449

ABSTRACT:
A level shifter circuit which is suitable for use in an integrated circuit converts an input logic signal having a first voltage potential to an output logic signal having a second voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages, the level shifter circuit allows reliable circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having a higher voltage potential, the same voltage potential, or a lower voltage potential. The level shift circuit includes an inverter stage which drives a fully differential output stage, and the fully differential output stage includes two sections. Each section incorporates a fast switching pair of transistors connected in series across an output supply voltage and ground potential which act as an inverter and which provide an output node at the series connection. For a section, the series-connected transistor between the output supply voltage and the output node is also connected in parallel with a voltage pull-up transistor having its gate controlled by the signal provided at the output node of the other section. The first section is controlled by the input logic signal provided to the gate of the series-connected transistor between its output node and the ground potential and the inverted input logic signal provided to the gate of the series-connected transistor between its output node and the output supply voltage. Similarly, the second section is controlled by the inverted input logic signal provided to the gate of the series-connected transistor between its output node and the ground potential and the input logic signal provided to the gate of the series-connected transistor between its output node and the output supply voltage.

REFERENCES:
patent: 4704547 (1987-11-01), Kirsh
patent: 4958091 (1990-09-01), Roberts
patent: 5321324 (1994-06-01), Hardee et al.
patent: 5479116 (1995-12-01), Sallaerts et al.
patent: 5583454 (1996-12-01), Hawkins et al.
patent: 5668483 (1997-09-01), Roohparvar

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