Universal logic chip

Details Universal logic chip Universal logic chip

1999-06-04

2002-12-17

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S082000

Reexamination Certificate

active

06496033

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to functionality of an integrated circuit and, more particularly, to selecting one of a set of possible functionalities or attributes of an integrated circuit chip via the connections to the chip.
BACKGROUND OF THE INVENTION
Conventional approaches to modifying the functionality of a chip or one of its attributes after fabrication include techniques such as burning through an element on the chip with a laser or a chemical means. However, conventional approaches generally must configure the chip prior to the completion of the packaging process (e.g., sealing the chip in its package).
Similarly, it may be desirable to change some part of the function of the chip such as by converting a simple buffer to a more complex register or to modify an electrical attribute of the chip (e.g., whether an input pin has bus-hold or not). In conventional approaches this type of modification is generally done by changing one or more of the actual interconnect layers of the chip so that the underlying transistors are connected in a different manner. This generally must be done during fabrication of the IC, and not by post-fabrication configuration.
In general, integrated circuits include pads that may be connected to bond wires that may electrically connect the chip to the pins of a package, lead frame or substrate on which the chip is mounted. A pad on an integrated circuit may or may not have a bond wire connecting the pad to a package pin which itself may be connected to a supply voltage (e.g., VCC) or ground or any other electrical signal.
Referring to
FIG. 1
, a package interconnection
10
is shown. The package interconnection
10
generally comprises a pad
12
on the chip, a bond wire
14
, a package pin
24
, an input buffer
16
, a chip interconnect wire
18
, a node
20
and a resistor
22
. The circuitry (not shown) connected to the output of the input buffer
16
is normally biased in the opposite voltage to that which the bond wire
14
is connected via the package pin
24
. For example, the circuitry connected to the output of the input buffer
16
may see the pad
12
as being connected to ground if the bond wire
14
is connected to a grounded package pin. Otherwise, the circuitry will see the pad as connected to the supply voltage VCC at the node
20
. In general, such a technique may be used to select between two operational modes on the circuit. For example, the selection between the normal operating mode of the chip and a special operating mode (e.g., a testing mode) may result. Alternatively, bond pads may receive an external signal that selects between two different electrical operating modes of a chip. For example, the chip may have a chip enable mode which turns off the chip's output buffers.
Once the chip is packaged, the functionality and basic electrical attributes generally cannot be changed. As a result, the end user generally loses the ability to change the functionality or electrical attributes of the chip after the device is packaged. This, in turn, generally requires the end user (or their supplier) to maintain a sufficient inventory of parts to provide all of the desired chip functions (e.g., buffer, inverter, register, latch, etc.), or basic electrical attributes (e.g., power supply voltage may be 5v, 3.3v, 2.5v etc.).
SUMMARY OF THE INVENTION
The present invention concerns an integrated circuit or chip having a number of bond pads or inputs that may or may not have a bond wire connecting the pad to a supply voltage, ground or via a package pin to an external input when the chip is placed in the package. The circuits such as the input buffer connected to the pad are normally biased in the opposite voltage to that which the bond wire may be connected. For example, the input buffer circuitry connected to the bond pad, may see the pad as being connected to ground if the bond wires are connected, otherwise the input buffer circuitry will see the pad as being connected to VCC. When the pad is connected to a package pin then the end user may apply an electrical signal (e.g., supply voltage or ground) so that the integrated circuit may be configured as any one of a number of possible devices having one of a set of electrical attributes. Typically, the chip will have up to 8 such pads which can be used individually or in combination to configure the device. In one example, the chip would be part of an existing ‘family’ of chips which all have, for example, N package pins. The extra package pins used to configure the chip would be added to one or both ends of the package so that the rest of the package looks like a normal non-configurable member of the ‘family’.
The objects, features and advantages of the present invention include a circuit and method that may change or determine the format, functionality, mode or electrical attributes of a device including three or more of the following attributes: (i) synchronous or asynchronous data transfer; (ii) registered or unregistered data transfer; (iii) one of a set of output drive strengths which may be balanced or unbalanced (e.g., +64 mA and −32 mA, or +24 mA, or +8 mA and −8 mA etc.), (iv) whether the inputs have ‘bus hold’ functionality or not and/or (v) one of 2
n
functions for the chip (for example, selecting between a buffer and a register).


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