Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-03-08
2005-03-08
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000, C326S063000, C327S333000
Reexamination Certificate
active
06864707
ABSTRACT:
Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies accommodate packaged devices that have at least three external pins, two pins for the coupling of a differential input signal, and a pin for the termination pair center tap.
REFERENCES:
patent: 6037798 (2000-03-01), Hedberg
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6603329 (2003-08-01), Wang et al.
3.2.7 Receiver Input Impedance, IEEE Std 1596.3-1996 (IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Computer Society, Jul. 31, 1996).
Pratt Stephen J. B.
Wong Thomas S.
Bachand Edward N.
Cho James H.
Dorsey & Whitney LLP
Micrel Incorporated
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