Universal impedance control for wide range loaded signals

Details Universal impedance control for wide range loaded signals Universal impedance control for wide range loaded signals

2000-09-29

2002-09-03

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000, C341S115000

Reexamination Certificate

active

06445316

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to digital circuits. In particular, the invention relates to impedance control.
2. Description of Related Art
Impedance controlled buffers are used in high-speed interfaces to improve signaling quality. Impedance of input/output (I/O) buffers changes with several factors including type of process, junction temperature, die temperature profile, noise, power supply fluctuations, device age, warm-up variations, etc. When a circuit involving I/O drivers is functioning, these changes in the impedance of the individual I/O drivers cause undesirable effects such as noise, reflections, crosstalk, ringing, overshoots and undershoots. The I/O buffer impedance can be controlled using analog or digital techniques. Digital control is the preferred method where compensation codes are used to compensate for any impedance mismatches at the pads of the I/O drivers. One method is referred to as resistor compensation (RCOMP) where an external reference resistor sets the impedance of the buffer. To maintain reasonable balanced impedance, compensation codes are recalculated and updated periodically.
Current techniques for updating compensation code are static in that the compensation codes are sent to the I/O drivers at a fixed, predetermined schedule. One approach is to update using a special reserved cycle (SRC). At designated times, the SRC is initiated, the transmission of data on the bus is stopped and the I/O drivers are tri-stated or put into an idle state. Then, the updated compensation codes are sent to the I/O drivers. This approach has a number of disadvantages. First, the transmission of data is temporarily suspended, resulting in a reduced transmission rate. Second, special circuitry is required to initiate the SRC. Third, the core of the device has to have some routing mechanism to route pending transactions into queues prior to code update. This approach therefore results in complex circuitry and degraded performance.


REFERENCES:
patent: 6297677 (2001-10-01), Ang et al.

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