Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1998-07-31
2001-06-05
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S210000, C257S207000, C257S691000, C257S200000, C257S208000
Reexamination Certificate
active
06242814
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor die pad structures having traditional in-line pad cell design with each cell supporting multiple pad sites and, more particularly, to cell pad designs that are universal in application and take advantage of the power and ground ring locations that are a common architecture for integrated circuit design.
2. Description of Related Art
Traditional semiconductor die design provides for a single array of I/O bonding or pad sites arranged around the periphery of the die. For a typical wire-bonded package design, these bonding sites, also referred to as pads, are connected to a lead frame by gold wires connecting to each desired site. The bonding sites consist of signal sites, Vss (ground or lower power) sites and Vdd (power or upper power) sites. A prior art signal and power/ground pin arrangement is illustrated in
FIG. 1
, where the signal
20
, Vss (ground)
30
and Vdd (power)
40
pins are placed in line as a single array, each consuming an I/O cell site
10
.
FIG. 1
shows four I/O cell sites
10
which, in a standard prior art die design, would be located with a number of similar cell sites around the periphery of the die. Most die pad designs use somewhere between 10 and 30 percent of the available integrated circuit (IC) pins for Vdd bond sites
40
and Vss bond sites
30
.
The minimum size of the I/O cell sites
10
and bond pads
20
,
30
,
40
is limited by current bonding technology. Consequently, increasing the number of signal bond sites
20
may require an increase in the size of the die to accommodate the signal bond sites
20
along with the Vss bond sites
30
and Vdd bond sites
40
in the traditional I/O designs.
I/O pads on a semiconductor logic product are becoming increasingly dense, which increases the difficulty of wire-bonding. Flip-chip technology addresses this problem to some extent by eliminating the wire-bonding step, allowing closer spacing of bond pad sites. A pad structure optimized for wire-bonding, however, may not be optimal for flip-chip assembly processing and vice-versa. Some integrated circuit products may need to be available in both traditional wire-bonded QFP packages and newer flip-chip BGA packages where an optimal solution using traditional bond pad design is difficult. Although a standard lead frame can be used with most wire-bonded packages, the accepting frame on a flip-chip package might need to be designed to accommodate the unique x/y coordinates of the solder ball layout. Consequently, designing a library of I/O cells to accommodate both assembly processes optimally often proves to be very difficult. The alternative, unique designs for different applications, can be very expensive.
The requirement for power and ground pins on complex semiconductor logic products is also increasing. Consuming valuable I/O pad space with a Vdd or Vss pad sites can be costly and may increase the size of the die if the die is pad-limited. A need exists, therefore, to accommodate more Vdd and Vss I/O connections without correspondingly increasing the die size. Ideally, this need should be addressed with a design that takes advantage of the traditional location of Vdd and Vss bus rings, thus reducing manufacturing costs and simplifying design considerations.
Accordingly, a need exists for a universal I/O pad structure design for in-line or staggered wire-bonding or arrayed flip-chip assemblies which will optimize the I/O cell to signal bond site ratio and provide a universal design for the placement of Vss and Vdd pad sites. This approach would alleviate the need to go to larger chip design to accommodate additional signal bond sites and make chip designs more uniform, thus greatly reducing manufacturing and design costs.
SUMMARY OF THE INVENTION
This invention proposes I/O cell bond site designs incorporating the advantages of the power and ground ring location, which is common architecture for integrated circuit design. The present invention utilizes multiple rows, in depth, of bond sites placed either staggered or in-line on the I/O cells. Common to each embodiment is the principal that all of the bond sites nearest the periphery of the die should be dedicated to signal bond sites, thereby increasing the efficiency of bond site placement. In addition, each embodiment of the present invention utilizes arrays of interior bond sites dedicated to Vss and Vdd pins which are interior to the signal bond sites, thus taking advantage of the underlying power and ground ring location common to many IC design chips. This invention provides increased bond mapping flexibility, simplicity, and uniformity in manufacture and design, and permits additional signal pad sites for given chip size.
Another feature of this invention allows for a universal design of a semiconductor die for use in both a traditional wire-bonding assembly and a flip-chip assembly. Since the exterior array on the die is dedicated exclusively to signal sites and the interior arrays are dedicated to Vss and Vdd sites, a die configured for a traditional wire-bonded package can easily be converted for use in a flip-chip BGA package. In fact, every Vdd and Vss site on the die could be soldered to the flip-chip accepting frame. This design would, consequently, avoid the need for expensive custom package design.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
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LSI Logic Corporation
Williams Alexander O.
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