Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-17
2006-01-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06988252
ABSTRACT:
An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.
REFERENCES:
patent: 5787010 (1998-07-01), Schaefer et al.
patent: 6107819 (2000-08-01), Doyle
Nanda et al., “A New Methodology for the Design of Asynchronous Digital Circuits,” IEEE, Jan. 1997, pp. 342-347.
Andreev Alexander E.
Scepanovic Ranko
LSI Logic Corporation
Siek Vuthe
Westman Champlin & Kelly
LandOfFree
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