Universal cost reduced substrate structure method and apparatus

Details Universal cost reduced substrate structure method and apparatus Universal cost reduced substrate structure method and apparatus

1996-08-20

1999-08-31

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438108, 438111, 257685, 257700, 257723, H01L 2144, H01L 2334

Patent

active

059465522

ABSTRACT:
A universal substrate includes an input/output (I/O) layer having a fixed I/O assignment of I/O locations for connection with a printed circuit board or the like. A chip receiving layer is provided for receiving one of at least two different but allied semiconductor chips, wherein each of the at least two different but allied chips include a set of bond pads and have a unique wire-out requirement. A first layer includes a plurality of bond pads and vias, the plurality of bond pads including at least two sets of bond pads, wherein each set is adapted for bond connection with a respective one of the at least two different semiconductor chips when received by said receiving means and further in accordance with a respective wire-out requirement. A second layer, different from the first layer, includes redistribution lines for coupling the plurality of bond pads and vias of the first layer to the I/O locations of the I/O layer in accordance with the wire-out requirements of the at least two different semiconductor chips and the fixed I/O assignment.

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