Unit semiconductor chip and multi chip package with center...

Details Unit semiconductor chip and multi chip package with center... Unit semiconductor chip and multi chip package with center...

2008-06-24

2008-06-24

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C438S109000, C438S613000, C257S786000, C257SE25006

Reexamination Certificate

active

07391105

ABSTRACT:
A unit semiconductor chip and stacked semiconductor package and method of manufacturing with center bonding pads and at least one circuit layer to reduce the length of bonding. The unit semiconductor chip includes a first series of bonding wires connected to a plurality of center bonding pads of a semiconductor chip, at least one circuit layer connected to the first series of bonding wires and including a series of circuit layer wiring patterns, and a second series of bonding wires connecting the series of circuit layer wiring patterns and a series of wiring patterns. The stacked semiconductor package further includes a second series of wiring patterns, connected to the first series of wiring patterns, the a second series of wiring patterns and the series of circuit layer wiring patterns providing connections to adjacent lower and upper unit semiconductor packages, respectively.

REFERENCES:
patent: 6404044 (2002-06-01), Akram et al.
patent: 6407448 (2002-06-01), Chun
patent: 6445064 (2002-09-01), Ishii et al.
patent: 6876074 (2005-04-01), Kim
patent: 7026709 (2006-04-01), Tsai et al.
patent: 2002/0027295 (2002-03-01), Kikuma et al.
patent: 2005/0104182 (2005-05-01), Kim
patent: 2000-228468 (2000-08-01), None
patent: 10-2001-0027266 (2001-04-01), None
patent: 10-2001-0068514 (2001-07-01), None
patent: 2003-0029743 (2003-04-01), None
Korean Patent Office Communication dated Jun. 29, 2005, for Korean Application No. 10-2003-0059834, with English Translation.

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