Unit cell layout and transfer gate design for high density DRAMs

Details Unit cell layout and transfer gate design for high density DRAMs Unit cell layout and transfer gate design for high density DRAMs

1994-11-15

1999-08-10

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257302, 257303, 257304, 257305, 257346, 257377, H01L 2170

Patent

active

059362715

ABSTRACT:
A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the trench capacitor and the bit line and a gate electrode formed by the active word line.

REFERENCES:
patent: 4710789 (1987-12-01), Furutani et al.
patent: 4829017 (1989-05-01), Malhi
patent: 4959698 (1990-09-01), Shinichi et al.
patent: 4961095 (1990-10-01), Mashiko
patent: 5012308 (1991-04-01), Hieda
patent: 5066609 (1991-11-01), Yamamoto et al.
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5244824 (1993-09-01), Sillan
patent: 5336916 (1994-08-01), Chen et al.
patent: 5543652 (1996-08-01), Ikeda et al.
patent: 5596212 (1997-01-01), Kuriyama
patent: 5606189 (1997-02-01), Adan

Affiliated with

Also associated with

Rating

Unit cell layout and transfer gate design for high density DRAMs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Unit cell layout and transfer gate design for high density DRAMs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Unit cell layout and transfer gate design for high density DRAMs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1122423