Unified stacked contact process for static random access memory

Fishing – trapping – and vermin destroying

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437 48, 437918, H01L 218244

Patent

active

056521740

ABSTRACT:
A method is provide for a unified stacked contact structure which concurrently forms all the polysilicon interconnects and the polysilicon load resistors on a SRAM device. FETs formed from a first polysilicon layer are coated with a first insulating layer. A second polysilicon layer is deposited and patterned forming portions of the SRAM circuit and concurrently forming openings over FET source/drain areas. A second insulating layer is deposited, and contact openings are selectively etched in the insulating layer over the openings in the second polysilicon layer. The exposed second polysilicon layer in the contacts serve as an etch mask for etching the first insulating layer to the source/drain contact areas, thereby forming contacts self-aligned to the openings in the second polysilicon layer. The contact openings in the node contact areas also expose portions of the gate electrodes .of the SRAM driver transistors. The unified stacked contacts are completed by depositing and patterning a conformal third polysilicon layer that forms interconnections in the contact openings between the exposed patterned polysilicon layers, and the third polysilicon layer is also patterned to form the polysilicon load resistors. The number of masking and other process steps are substantially reduced.

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patent: 4968645 (1990-11-01), Baldi et al.
patent: 4980732 (1990-12-01), Okazawa
patent: 5168076 (1992-12-01), Godinho et al.
patent: 5200356 (1993-04-01), Tanaka
patent: 5474948 (1995-12-01), Yamazaki

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