Unified SRAM cache system for an embedded DRAM system having...

Details Unified SRAM cache system for an embedded DRAM system having... Unified SRAM cache system for an embedded DRAM system having...

2005-04-05

2005-04-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S225700

Reexamination Certificate

active

06876557

ABSTRACT:
A unified SRAM cache system is provided incorporated several SRAM macros of an embedded DRAM (eDRAM) system and their functions. Each incorporated SRAM macro can be independently accessed without interfering with the other incorporated SRAM macros within the unified SRAM cache system. The incorporated SRAM macros share a single set of support circuits, such as row decoders, bank decoders, sense amplifiers, wordline drivers, bank pre-decoders, row pre-decoders, I/O drivers, multiplexer switch circuits, and data buses, without compromising the performance of the eDRAM system.

REFERENCES:
patent: 5226009 (1993-07-01), Arimoto
patent: 5509132 (1996-04-01), Matsuda et al.
patent: 6510492 (2003-01-01), Hsu et al.

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