Unified placer infrastructure

Details Unified placer infrastructure Unified placer infrastructure

2006-01-03

2006-01-03

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06983439

ABSTRACT:
Method and apparatus are described for a placer system for placing design objects onto an arrayed architecture, such as a programmable logic device including an FPGA. More particularly, a placer interface is described for communicating with a placer core. The placer interface receives information from external entities, and unifies and generalizes this information for the placer core. The external entities comprise different representations of architecture, design, device, constraints and algorithm-dictated placer-movable objects.

REFERENCES:
patent: 6631508 (2003-10-01), Williams
patent: 6704915 (2004-03-01), Andreev et al.
patent: 6721935 (2004-04-01), Morinaga

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