Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-05-21
2002-08-06
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S129000, C711S173000, C711S113000, C710S056000
Reexamination Certificate
active
06430660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of data storage. More particularly, the present invention relates to a memory configuration for a hard disk drive controller system.
2. Description of the Related Art
FIG. 1
shows an exemplary hard disk drive (HDD) system
10
having a conventional hard disk controller (HDC) system
20
. HDD system
10
includes a hard disk
11
on which data is stored, an arm
12
, a read/write head
13
, an arm electronics (AE) circuit
14
and a hard disk controller (HDC) system
20
. HDC system
20
is connected to read/write head
13
through AE circuit
14
by way of a disk channel path
16
and to a host computer system
18
through a host communications path
17
.
FIG. 2
shows a schematic block diagram of a memory arrangement for a conventional HDC system
20
.
FIG. 2
shows that system
20
includes a hard disk controller (HDC)
21
, an HDC buffer, or cache, memory
22
, a microprocessor (&mgr;P)
23
, a Read-Only Memory (ROM) instruction memory
24
for microprocessor
23
, and a writable Random Access Memory (RAM)
25
.
Requests for access to the memories of memory of HDC system
20
originate from four different sources: hard disk controller
21
, microprocessor
23
, disk channel path
16
and host communications path
17
. Disk channel path
16
is the path by which data is written to and recovered from disk
11
. Host communications path
17
is the interface for HDD system
20
with host system
18
. Both hard disk controller
21
and microprocessor
23
tend to access the various memory spaces in a relatively diffuse pattern over widely separated positions within the memory spaces. Microprocessor
23
accesses HDC buffer memory
22
only by way of requests to hard disk controller
21
, with data being passed by using registers within hard disk controller
21
. In contrast to hard disk controller
21
and microprocessor
23
, both disk channel
16
and host communications path
17
are high-speed interfaces capable of accessing many sequential positions of memory at a time.
Each of the different memory spaces of system
10
are conventionally provided on physically separate integrated circuit substrates, or chips. The physical separation of each memory is represented in
FIG. 2
by dashed lines appearing around the respectively different components of system
20
. For example, RAM
25
is separate from ROM
24
, while ROM
24
conventionally is combined with microprocessor
23
on a single chip.
The physical separation of the memories is required because each respective memory space is fabricated using different technology, such as different mask levels and processing steps, and has a corresponding different operational performance characteristics. For example, HDC cache memory
22
requires a high bandwidth and capacity that is similar to that provided by dynamic RAM (DRAM) technologies. The ROM instruction memory
24
must be non-volatile, such as provided by ROM- or Flash-type memories. Finally, RAM
25
for microprocessor
23
must have a fast access and cycle time as provided by Static RAM (SRAM) memory. Additionally, the DRAM-, ROM- and Flash-type memories of
FIG. 1
have processing steps that conflict with the normal processing of the logic devices of HDC system
20
. When the processing steps for the memories are combined with the processing steps for the logic devices, performance compromises occur.
Occasionally, the memory granularity for each of the three different memory types used for a conventional HDC system does not match the requirements of the HDD and causes the system design to use more expensive memories than are optimal. The frequency of occurrence of a granularity mismatch between a conventional HDC memory and the requirements for an HDD system increases with time and will likely occur a twice as frequent or more within several years for desktop PC HDDs.
What is needed is a memory configuration that optimizes memory space within an HDC system.
SUMMARY OF THE INVENTION
The present invention provides a memory configuration that optimizes memory space within an HDC system. The advantages of the present invention are provided by a disk controller system that includes a microprocessor, a hard disk controller, a disk channel path, a host communications path, and an interface coupled to each of the microprocessor, hard disk controller, disk channel path and host communications path. A unified non-volatile memory is coupled to the interface that has a plurality of memory spaces. Preferably, the unified memory is formed from an array of magnetic tunnel junction memory cells. A memory space is allocated for each of the microprocessor, hard disk controller, disk channel path and host communications path. Each memory space is separated from another memory space by a programmable memory space boundary. According to the present invention, the microprocessor, hard disk controller and the unified memory are all fabricated on a single substrate.
The present invention also provides a method for controlling memory space in a unified memory of a disk controller system in which a first memory space is established in the unified memory. A second memory space is established in the unified memory, with the first and second memory spaces being separated by a memory space boundary. The memory space boundary is then changed with respect to the first and second memory spaces in response to an operational requirement of the disk controller system, such as a detected operational condition or a command received from a host system to the disk controller system. Accordingly, a third memory space can be established in the unified memory, with the third memory space being separated from one of the first and second memory spaces by a second memory space boundary. In this situation, the second memory boundary is changed in response to the operational requirement of the disk controller.
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Kemp Timothy Michael
Palmer John Davis
Scheuerlein Roy Edwin
Banner & Witcoff , Ltd.
Berthold, Esq. Thomas R.
Portka Gary J.
Yoo Do Hyun
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