Unified layer stack architecture

Details Unified layer stack architecture Unified layer stack architecture

2008-04-25

2010-12-14

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07853901

ABSTRACT:
A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

REFERENCES:
patent: 2003/0067075 (2003-04-01), Fukasawa
patent: 2005/0198608 (2005-09-01), Brown
patent: 2006/0165813 (2006-07-01), Dangel et al.
patent: 2008/0201685 (2008-08-01), Selvaraj
patent: 2009/0134909 (2009-05-01), Madurawe

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