Uni-transistor random access memory device and control...

Details Uni-transistor random access memory device and control... Uni-transistor random access memory device and control...

2003-02-03

2004-05-11

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S203000

Reexamination Certificate

active

06735109

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a static random access memory device using two DRAM cells as one memory cell.
2. Discussion of Related Art
FIG. 1
shows a uni-DRAM cell structure. In
FIG. 1
, two of the DRAM cells (MC
1
, MC
2
) or memory cells are illustrated. Each of the DRAM cells includes one cell transistor TR and one cell capacitor C. In a DRAM cell MC
1
, a gate of the cell transistor is coupled to a wordline WL
1
, and a current path of the cell transistor is formed between a bitline BL and one electrode of the cell capacitor. The other electrode of the cell transistor is coupled to a voltage Vp. In a DRAM cell MC
2
, a gate of the cell transistor is coupled to a wordline WL
2
, and a current path of the cell transistor is formed between a bitline BLB and one electrode of the cell capacitor. The other electrode of the cell capacitor is coupled to the voltage. The bitlines (BL, BLB) are coupled to a sense amplifier
12
.
In the DRAM cell structure of
FIG. 1
, when the wordline WL
1
is selected, cell data stored in the cell capacitor of the DRAM cell MC
1
is transferred to the bitline BL by means of charge sharing. Typically, the bitlines (BL, BLB) are precharged to half a power supply voltage for an array (AIVC), i.e., AIVC/2, prior to a sensing operation. A potential of the bitline BL is increased or decreased by the charge sharing. When data of “1” is stored in the memory cell MC
1
, the potential of the bitline is increased by the charge sharing. When data of “0” is stored in the memory cell MC
1
, the potential of the bitline is decreased by the charge sharing. In this case, the sense amplifier
12
senses and amplifies a potential difference between the bitlines (BL, BLB).
It is well known in the art that since cell data may be damaged by leakage current resulting from the characteristic of the DRAM cell structure, electric charges stored in a cell capacitor may be reduced. For this reason, a potential difference between the bitlines is reduced such that it is impossible to carry out a normal sensing operation, and a refresh fail occurs. Thus, the DRAM cell structure requires a refresh operation for maintaining stored data. A refresh cycle of a DRAM cell comprising one cell capacitor and one cell transistor is determined on the basis of a refresh time (t
REF
) of cell data “1”. Here the “refresh time” means the maximum time that data stored in a memory cell can be maintained.
One way to realize a reduced power consumption in a semiconductor memory device adopting a DRAM cell structure is to prolong a refresh time or cycle. The refresh time or cycle may be extended by adopting a twin cell structure. A twin cell structure well known in the art is illustrated in FIG.
2
.
Referring to
FIG. 2
, a twin cell includes two DRAM cells (MC
1
, MC
2
) each having one cell transistor and one cell capacitor. In the DRAM cell MC
1
, a gate of the cell transistor is coupled to a wordline WL
1
. A current path of the cell transistor is formed between a bitline BL and one electrode of the cell capacitor. The other electrode of the capacitor is coupled to a voltage Vp. In the DRAM cell MC
2
, a gate of the cell transistor is coupled to the wordline WL
1
. A current path of the cell transistor is formed between a bitline BLB and one electrode of the cell capacitor. The other electrode of the capacitor is coupled to the voltage Vp. The bitlines (BL, BLB) are coupled to a sense amplifier
22
. DRAM cells constituting the twin cell store complementary data. For example, when the DRAM cell MC
1
stores cell data “1”, the DRAM cell MC
2
stores cell data “0”. On the other hand, when the DRAM cell MC
1
stores cell data “0”, the DRAM cell MC
2
stores cell data “1”.
Referring to
FIG. 3
showing another twin cell structure, each of DRAM cells (MC
1
-MC
4
) has one cell transistor and one cell capacitor. In the DRAM cell MC
1
, a gate of the cell transistor is coupled to a wordline WL
1
. A current path of the cell transistor is formed between a bitline BL
1
and one electrode of the cell capacitor. In the DRAM cell MC
2
, a gate of the cell transistor is coupled to the wordline WL
1
. A current path of the cell transistor is formed between a bitline BL
3
and one electrode of the cell capacitor. The bitlines (BL
1
, BL
3
) are coupled to a sense amplifier
32
. The DRAM cells (MC
1
, MC
2
) constitute a twin cell. In the DRAM cell MC
3
, a gate of the cell transistor is coupled to a wordline WL
2
. A current path of the cell transistor is formed between the bitline BL
2
and one electrode of the cell capacitor. In the DRAM cell MC
4
, a gate of the cell transistor is coupled to the wordline WL
2
. A current path of the cell transistor is formed between the bitline BL
4
and one electrode of the cell capacitor. The bitline (BL
2
, BL
4
) are coupled to a sense amplifier
34
. The DRAM cells (MC
3
, MC
4
) constitute a twin cell. DRAM cells each constituting a twin cell store complementary data. Thus, a semiconductor memory device adopting the twin cell structure has a longer refresh cycle or time than a semiconductor memory device adopting a uni-cell structure. This is explained in detail below.
FIG. 4
is a circuit diagram showing a conventional sense amplifier, and
FIG. 5
is a timing diagram for explaining a read operation of an SRAM device having a twin cell structure. The read operation of the SRAM device is now described with reference to
FIG. 2
,
FIG. 4
, and FIG.
5
. Prior to activation of a wordline WL
1
, bitlines BL and BLB are precharged to a precharge voltage VBL, i.e., AIVC/2, through a bitline precharge unit
30
. It is assumed that cell data “1” is stored in a DRAM cell MC
1
and cell data “0” is stored in a DRAM cell MC
2
. Under this assumption, a node CN
1
, i.e., a connection node of a cell capacitor and a transistor, of the DRAM cell MC
1
has a power supply voltage (AIVC) corresponding to the cell data “1”, and a cell node CN
2
of the DRAM cell MC
2
has a ground voltage GND corresponding to the cell data “0”. As the wordline WL
1
is activated, charge sharing is established between the bitline BL and a cell capacitor of the DRAM cell MC
1
as well as between the bitline BLB and a cell capacitor of the DRAM cell MC
2
. From the charge sharing, a voltage of the bitline BL is increased by voltage V
CS
(meaning a voltage gained by subtracting a precharge voltage VBL from a charge-shared bitline voltage) and a voltage of the bitline BLB is decreased by the voltage V
CS
, as shown in FIG.
5
.
Following the charge sharing operation, when a voltage difference between the bitlines (BL, BLB) is sufficiently amplified, a column selection line CSL is activated, as shown in FIG.
5
. As the column selection line is activated, input/output lines and the bitlines are electrically connected to each other. Since an input/output line having a high loading capacitance is precharged to internal power supply voltage IVC, voltages of the bitline BLB and the cell node CN
1
, which drop toward the ground voltage, are clamped to a specific voltage level. In this case, the voltages of the bitline and the cell node are scarcely affected by the activation of the column selection line. Following inactivation of the column selection line, voltages of the bitline BLB and the cell node CN
2
drop to the ground voltage. If the cell data “1” and the cell data “0” are re-stored in the cell nodes (CN
1
, CN
2
) according to the voltages of the bitlines (BL, BLB), the wordline WL
1
is inactivated and the bitlines are precharged to the precharge voltage VBL.
As described above, since DRAM cells each constituting a twin cell store complementary data, a double voltage difference is made between bitlines as compared to a uni-cell structure. As shown in
FIG. 5
, the bitline BL coupled to the DRAM cell MC
1
storing the cell data “1” is increased by V
CS
by way of the charge sharing, while the bitline BLB coupled to the DRAM cell MC
2
storing the cell data “0” is decreased by V
CS
by way of the charg

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