Uni-sized clock buffers

Details Uni-sized clock buffers Uni-sized clock buffers

2001-10-25

2003-06-10

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S101000, C327S295000, C327S297000

Reexamination Certificate

active

06577165

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to clock buffer trees, and more specifically relates to a new clock buffer tree wherein all of the clock buffers have the same pin-outs, thereby providing that it is relatively easy to upsize or downsize any of the clock buffers in the tree.
BACKGROUND OF THE INVENTION
A clock buffer tree allows a single clock source to effectively drives thousands of Flip-Flops. Specifically, one clock buffer may drive four clock buffers, and those four clock buffers drive sixteen clock buffers until the clock buffer is strong enough to drive the desired number of Flip-Flops. However, no matter how many clock buffers there are in a clock buffer tree, there are clock skew problems due to the fact that the clock tools are never perfect. Ideally, the smaller the clock skew, the less problem there is for setup and hold times. Hence, less effort is required to perform Static Timing Analysis (STA), and less time is needed to tune the clock in the layout. However, in reality, initially there is always a clock skew problem of some sort.
FIGS. 1-3
illustrate the potential setup and hold time problems when clock skew is encountered. Specifically,
FIG. 1
shows the typical Flip-Flop to Flip-Flop path.
FIG. 2
shows how clock skew may effect Setup.
FIG. 2
shows the situation where the skew is negative, the logic delay is large, the Relative Cycle Time is equal to the clock cycle minus skew, and the Setup margin is subtracted by the clock skew.
FIG. 3
is similar to
FIG. 2
, and shows how clock skew may effect Hold.
FIG. 3
shows the situation where the skew is positive, the logic delay is minimal, and the Hold margin is subtracted by the clock skew.
When designing ASIC's, different strength clock buffers are typically used to combat clock skew problems. In other words, clock buffer trees have clock buffers of different strengths mixed in throughout the clock buffer tree. For example, a clock buffer tree may include “A” strength, “B” strength, “C” strength . . . and “F” strength clock buffers, wherein “A” strength clock buffers have lower drive strength than “B” strength clock buffers, and “B” strength clock buffers have substantially lower drive strength than “F” strength clock buffers, which have very a strong drive strength.
A problem with including clock buffers of different strengths within a clock buffer tree is that clock buffers of different strengths do not have the same pin-outs. In other words, clock buffers of different strengths consume different amounts of real estate on the chip. Hence, it may be difficult, after designing the clock buffer tree, to upsize any of the clock buffers in the tree. The difficulty may arise because there may be congestion around the clock buffers. In such case, it would be difficult to replace one sized clock buffer with another sized clock buffer in the clock buffer tree, and it may be difficult to route to the new cell. This often dramatically slows the progress of layout design, and dramatically slows the performance of Static Timing Analysis (STA). In addition, adjacent cells and nets may have to be moved or re-routed as well as the nets which relate to the cell which is being upsized. This often makes the new result very unpredictable. In the end, cells may need to be upsized, downsized and move around the chip in order to arrive at a design which is satisfactory.
This clock tuning process is often very lengthy, repetitive, and can be frustrating to both the engineer designing the clock buffer tree and the layout person who is designing the overall layout.
OBJECTS AND SUMMARY OF THE INVENTION
A general object of an embodiment of the present invention is to provide a system which simplifies the clock tuning process for a clock buffer tree.
Another object of an embodiment of the present invention is to provide a clock buffer tree which has clock buffers of different strengths, but where the different strength clock buffers have the same pin-out configuration.
Still another object of an embodiment of the present invention is to provide a clock buffer tree that has a plurality of clock buffers which have different strengths but identical pin-out configurations.
By providing that a clock buffer tree has clock buffers of different strengths, but the same pin-out configuration, it is easy and straightforward to upsize or downsize any of the clock buffers in the clock buffer tree. Unlike in prior art configurations, it is guaranteed that the new cell will fit into the old cell's slot in the tree. Since none of the nets, including the cell being changed or any of the adjacent cells, needs to be modified, consistent timing results can be achieved. Moreover, the new timing for the modified clock buffer can be anticipated because its wire loading does not change at all. The ease of clock tuning makes it much easier to design clock buffer trees and layouts, and allows the overall design to be completed faster and easier.


REFERENCES:
patent: 5923188 (1999-07-01), Kametani et al.
patent: 6204713 (2001-03-01), Adams et al.
patent: 6313683 (2001-11-01), Block et al.
patent: 6356116 (2002-03-01), Oh

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