Undoped polysilicon gate process for NMOS ESD protection circuit

Details Undoped polysilicon gate process for NMOS ESD protection circuit Undoped polysilicon gate process for NMOS ESD protection circuit

1996-06-13

1998-07-21

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257357, 257364, 257369, 257412, 257413, 257360, H01L 2362

Patent

active

057838500

ABSTRACT:
An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped gate polysilicon electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.

REFERENCES:
patent: 4931411 (1990-06-01), Tigelaar et al.
patent: 5192992 (1993-03-01), Kim et al.
patent: 5468666 (1995-11-01), Chapman
patent: 5567642 (1996-10-01), Kim et al.

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