Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-14
2002-11-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S346000, C438S257000, C438S264000, C438S261000
Reexamination Certificate
active
06483159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to split gate, flash memory devices.
2. Description of Related Art
U.S. Pat. No. 5,532,178 of Liaw, for “Gate Process for NMOS ESD Protection Circuits” shows an undoped silicide gate in an ESD protection device for protecting doped silicide gate FET product device circuits, with no floating gates and no control gates, for a ESD device where an N implant is unwanted, e.g. in PMOS device areas. At col. 5, lines 49 et seq. Liaw states as follows: “The undoped polysilicon gates of the NMOS ESD circuit give the NMOS devices a higher breakdown voltage Vg that ensures that the ESD circuit will protect the product devices. The undoped polysilicon gate electrode . . . also allows the use of thinner gate oxides thereby increasing the speed of the product devices. That is to say that the ESD device protects the FET product devices so they can be made with thinner gate oxides because they will not be exposed to damaging ESD voltages.”
U.S. Pat. No. 4,698,787 of Mukherjee et al. for “Single transistor electrically programmable memory device and method”
U.S. Pat. No. 4,964,143 of Haskell for an EPROM element employing self-aligning process; U.S. Pat. No. 5,067,108 of Jenq for Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate; U.S. Pat. No. 4,599,706 of Guterman; U.S. Pat. No. 4,462,089 of Miida et al.; and U.S. Pat. No. 4,274,012 of Simko all show Electrically Erasable Programmable Read Only Memory (EEPROM) devices.
SUMMARY OF THE INVENTION
N+ doped polysilicon gate electrodes are used for almost all the floating gate of the nonvolatile memory cells. Although the split-gate Flash is well known for its higher programming speed, as the result of an effort directed to improving the programming speed we have found that the speed of programming is even faster by using the undoped polysilicon
1
as the material in the floating gate electrode.
An advantage of this new structure is that the threshold under the floating gate electrode is increased, which increases the immunity from punchthrough.
Another advantage of this new structure is that the programming speed is increased.
In accordance with this invention, a method of forming a split gate EEPROM memory device on a doped silicon semiconductor substrate comprises the steps which follow in accordance with the description relating to FIGS. 2A-2F in, commonly assigned U.S. Pat. No. 5,940,706 based upon U.S. patent application Ser. No. 08/988,764 filed Dec. 11, 1997 by the same inventors Hung-Cheng Sung, Di-Son Kuo, Yai-Fen Lin and Chia-Ta Hsieh for “Process for Preventing Misalignment in Split-Gate Flash Memory Cell” which is incorporated herein by reference.
Form an oxide layer upon the surface of the silicon substrate. Then, form an undoped first polysilicon layer upon the top surface of the oxide layer. Form a silicon nitride layer upon the top surface of the undoped first polysilicon layer. Next, form a photoresist mask for patterning the silicon nitride layer and then etch the silicon nitride layer through the openings in the photoresist mask, stopping on the undoped first polysilicon layer. Remove the photoresist. Then perform a polysilicon oxidation to form a polysilicon oxide hard mask for use in patterning the undoped first polysilicon layer and the oxide layer therebelow. Then remove the remainder of the silicon nitride layer. Next, etch down through the undoped first polysilicon layer and the gate oxide layer to form a floating gate electrode. Form a blanket tunnel oxide layer over the floating gate electrode stack and over the substrate aside from the floating gate electrode stack. Then, form a doped, second polysilicon layer over the tunnel oxide layer. Pattern the the second polysilicon layer and the blanket tunnel oxide layer using a mask and etching to form a split control gate electrode above the substrate and crossing over only one edge of the floating gate electrode stack. Form in the configuration of a split gate EEPROM memory device a source region associated with the floating gate stack and a drain region associated with the control gate stack.
Preferably, the oxide layer is composed of silicon dioxide (SiO
2
) and has a thickness from about 50 Å to about 100 Å. The undoped first polysilicon layer has a thickness from about 500 Å to about 1500 Å. The blanket tunnel oxide layer has a thickness from about 150 Å to about 300 Å. The floating gate electrode and the control gate electrode are in proximity along the sidewalls thereof.
In accordance with another aspect of this invention, a split gate EEPROM memory device is formed on a doped silicon semiconductor substrate. A floating gate electrode stack comprises undoped polysilicon to serve as a floating gate electrode and a dielectric layer formed on the substrate, and a control gate electrode stack with doped polysilicon and a second dielectric layer. The control gate electrode stack is located in a split-gate configuration with respect to the floating gate electrode stack.
In accordance with still another aspect of this invention, a split gate EEPROM memory device on a doped silicon semiconductor substrate comprises an oxide layer upon the surface of the substrate. There is an undoped first polysilicon layer upon the substrate. The oxide layer and the undoped first polysilicon layer are formed into a floating gate electrode stack with a concave upper surface formed on the floating gate electrode by polysilicon oxidation. There is a blanket tunnel oxide layer over the floating gate electrode stack and over the substrate aside from the floating gate electrode stack and a doped, second polysilicon layer over the tunnel oxide layer. The blanket tunnel oxide layer and the second polysilicon layer are patterned into a split control gate electrode above the substrate and crossing over only one edge of the floating gate electrode stack. The device is in the configuration of a split gate EEPROM memory device a source region associated with the floating gate stack and a drain region associated with the control gate stack.
Preferably, the oxide layer is composed of silicon dioxide and has a thickness from about 50 Å to about 100 Å. The undoped first polysilicon layer has a thickness from about 500 Å to about 1500 Å. The blanket tunnel oxide layer has a thickness from about 150 Å to about 300 Å. The floating gate electrode and the control gate electrode are in proximity along the sidewalls thereof.
REFERENCES:
patent: 4274012 (1981-06-01), Simko
patent: 4462089 (1984-07-01), Miida et al.
patent: 4599706 (1986-07-01), Guterman
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4964143 (1990-10-01), Haskell
patent: 5067108 (1991-11-01), Jeng
patent: 5532178 (1996-07-01), Liaw et al.
patent: 6171906 (2001-01-01), Hsieh et al.
patent: 6184088 (2001-02-01), Kurooka et al.
Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Sung Hung-Cheng
Yeh Juang-Ke
Ackerman Stephen B.
Jones II Graham S.
Le Thao P.
Nelms David
Saile George O.
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