Underfilling efficiency by modifying the substrate design of...

Details Underfilling efficiency by modifying the substrate design of... Underfilling efficiency by modifying the substrate design of...

2006-07-11

2006-07-11

Patel, Ishwar (I. B.) (Department: 2841)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S255000, C174S260000, C257S738000

Reexamination Certificate

active

07075016

ABSTRACT:
A substrate structure including a substrate with solder bumps on a main region and a peripheral region of a front side thereof; a solder mask is formed over the front side of the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern includes openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

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patent: 2002/0011656 (2002-01-01), Swanson et al.

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