Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1997-08-20
1999-09-28
Picardat, Kevin M.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438118, 438123, 438124, H01L 2144, H01L 2148, H01L 2150
Patent
active
059602589
ABSTRACT:
An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.
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Collins Devin
Micro)n Technology, Inc.
Picardat Kevin M.
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