Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-03
2003-04-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S136000, C257S138000, C257S139000, C257S141000, C257S173000, C257S175000, C257S331000
Reexamination Certificate
active
06555878
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electrostatic discharge (ESD) structures for sub-micron devices, and more particularly to a thyristor (silicon controlled rectifier) which is gated by a U-type gate structure of a MOS (UMOS) transistor.
2. Description of the Related Art
The Silicon Controlled Rectifier (SCR) is the most efficient of all protection devices in terms of ESD performance per unit area. Usually, the SCR trigger level is quite high. The Low Voltage Trigger SCR (LVTSCR) is the most promising device for ESD protection by surface channel to reduce the drain-tap junction avalanche breakdown. Recently, reports have shown that LVTSCR's with shallow trench isolation (STI), especially on epi, are not functional because the hole current cannot efficiently forward bias the n+ cathode/p-substrate junction. Also, the silicidation process for reducing electrostatic discharge (ESD) performance is still a concern and needs to be evaluated for deep-quarter-micron (1 micron=10
−6
meters) technologies. Therefore, it is very useful to invent a new type of thyristor structure with a low controllable trigger voltage that is compatible with self-aligned silicide and STI fabrication technology without adding any process complexity and cost.
Below are listed U.S. Patents which describe gate controlled SCR structures employing a Trench-Gated MOS (UMOS) structure that will provide a low trigger voltage to prevent damage during an ESD event are:
U.S. Pat. No. 5,940,689 (Rexer et al.), U.S. Pat. No. 5,682,048 (Shinohara et al.), and U.S. Pat. No. 5,324,966 (Muraoka et al.) each describe the structure of the Trench-Gated MOS device. Muraoka et al. describes this structure to implement a thyristor.
U.S. Pat. No. 5,576,557 (Ker et al.) describes a low voltage trigger SCR for application to an ESD protection circuit.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a MOS gate-controlled SCR (UGSCR) structure for an ESD protection circuit in an IC device that is compatible with shallow trench isolation (STI) and self-aligned suicide (salicide) fabrication technology without adding any process complexity and cost.
It is another object of the invention to provide a MOS gate-controlled SCR structure for an ESD protection circuit in an IC device, which can give a low clamping voltage in the order of 1 to 2 V for deep-quarter-micron (1 micron=10
−6
meters) process application.
It is yet another object of the present invention to provide the UGSCR with a low impedance state when “on”, of about 1 to 3 ohms to make the UGSCR a low power dissipating device-for ESD protection.
It is still another object of the present invention to provide a CMOS latchup immune circuit by insuring that the threshold voltage of the UMOS-like gate is larger than the Vdd voltage.
These and many other objects have been achieved by creating a structure and a method in which a parasitic thyristor (or SCR) has a UMOS-like gate structure. The UMOS-like gate structure consists of a U-type gate flanked on either side by an n-well or in the alternative by a p-well. The U-type gate is connected on one side to an adjacent p+ diffusion which is the anode. On the other side of the gate and also adjacent to it is an n+ diffusion which is the cathode. The latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
Note that the figures herein illustrate vertical cross sections of devices and that the devices extend laterally (into and/or out of the page) in a manner appreciated by those skilled in the art.
REFERENCES:
patent: 5324966 (1994-06-01), Muraoka et al.
patent: 5576557 (1996-11-01), Ker et al.
patent: 5682048 (1997-10-01), Shinohara et al.
patent: 5940689 (1999-08-01), Rexer et al.
Hua Guang ping
Lo Keng-Foo
Song Jun
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
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