Ultrascaled MIS transistors fabricated using...

Details Ultrascaled MIS transistors fabricated using... Ultrascaled MIS transistors fabricated using...

1999-04-14

2003-03-18

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S305000, C438S574000, C257S072000

Reexamination Certificate

active

06534348

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of fabricating MIS transistors and well as plural such transistors in a stacked relation.
2. Brief Description of the Prior Art
The continued downscaling of transistor geometries is limited by the drain-induced barrier lowering (DIBL) effect wherein, as the channel becomes increasingly thinner or shorter, the isolation between the drain and the source decreases, this leading to unacceptably high off-currents. Prior art attempts at avoiding this effect have utilized double gate or wrap-around transistors which minimize DIBL effects. However, the fabrication process for these transistors is very complex because of the very thin conduction layers and gate dielectric layer which are required, these layers having thicknesses on the order of 20 nanometers and 3 nanometers, respectively.
SUMMARY OF THE INVENTION
The above described problem of the prior art is minimized in accordance with the present invention.
Briefly, an MIS transistor is provided having a double gate using an entirely epitaxial approach. By using this epitaxial approach, the channel, gate dielectric and gate layers can be deposited with atomic layer control wherein the silicon and dielectric layers are of uniform thickness to avoid problems which may be caused by having breakdown from gate electrode to channel due to regions of insufficient gate dielectric thickness. Examples of lattice-matched materials include silicon, cobalt silicide for the gate and calcium fluoride (CaF
2
), cerium oxide (CeO
2
) or calcium strontium titanate (Ca
x
Sr
1−x
TiO
3
) for the dielectric. In addition, since the gate dielectric is lattice-matched to silicon, epitaxial deposition of silicon thereover is single crystal rather than arnorphous.
A fabrication process for a semiconductor device in accordance with the present invention includes providing a layer of single crystal silicon having a predetermined crystallographic orientation, the preferred embodiment having a (111) crystallographic orientation. This layer will act to provide substantially single crystal growth thereover and can be a substrate or an epitaxially deposited layer. The surface of the silicon is then cleaned in standard manner and a layer of a dielectric material which is lattice matched or substantially lattice matched to the silicon, preferably calcium fluoride (CaF
2
), cerium oxide (CeO
2
) or calcium strontium titanate (Ca
x
Sr
1−x
TiO
3
), is epitaxially deposited over the silicon, and for the case of CaF
2
, this layer being deposited at a rate of from about 10 to about 30 Angstroms per minute at a temperature of from about 550 to about 700 degrees C. to a thickness of from about 30 to about 100 Angstroms. At higher deposition rates for CaF
2
, the atoms of the dielectric have difficulty rearranging themiselves and therefore provide an inferior quality dielectric layer. At higher temperatures, the quality of the interface deteriorates whereas at lower temperatures the activity is too slow whereby the atoms again have difficulty rearranging themselves to provide a monocrystalline structure. A layer of electrically conductive material which is a first gate electrode is also lattice matched or substantially lattice matched to the silicon layer and dielectric layer, the gate electrode being preferably cobalt silicide (CoSi
2
). The cobalt silicide is epitaxially deposited over the dielectric layer by depositing about 300 Angstroms of silicon at about 500 degrees C., followed by about 150 Angstroms of cobalt at about 100 degrees C. at a rate of about 10 Angstroms per minute. The cobalt silicide layer is then formed by annealing the wafer or sample at about 500 degrees C. for from about 10 to 30 minutes. This two step process forms a flat and uniform CoSi
2
layer. The electrically conductive gate electrode material is then patterned and etched in standard manner to provide a gate structure and a further layer of dielectric material having a thickness of from about 30 to about 100 Angstroms is conformally deposited epitaxially under different conditions from the prior layer of dielectric material. To avoid undesirable reaction between the CoSi
2
and overlying CaF
2
, the CaF
2
should be deposited at a temperature of about 500 to 550 degrees C. (preferred), or by an ion beam deposition method, whereby separate ions of Ca and F are accelerated at the substrate at temperatures below 500 degrees C. This dielectric layer, preferably calcium fluoride, which is the first gate dielectric, is epitaxially deposited over the surface of the device being fabricated, the thickness being not so great that the lattice matching with the layers thereunder is not materially altered so that a layer of silicon having the same crystallographic structure as the initial layer of silicon can then be epitaxially deposited over the calcium fluoride and not so thin as to allow leakage from gate electrode to channel. A further layer of silicon, which will also be single crystal, is then epitaxially deposited over the first gate structure and the layers of dielectric and conductive material are repeated to provide the second gate structure and complete fabrication of the transistor.
Additional layers of silicon followed by layers of dielectric and conductive material as described above can then be epitaxially deposited to maintain the single crystal structure in a vertical direction one or more times to provide any number of stacked transistors, one atop the other, if more than one transistor is required. These additional transistors can be controlled by the gate structures on one or both sides thereof.
The source and drain regions for each of the above described embodiments are formed by etching away a portion of the dielectric layer and then forming the source and drain regions by patterning and implanting dopant on opposite sides of the gate structure and into the silicon layer under the gate structure in standard manner.
As alternative embodiments, the source and drain regions can extend to additional silicon layers and therefore form the source and drain of plural transistors, each controlled by its own gate electrode. The current-drive capabilities of such a vertically-integrated, multiple-gate transistor may have applications in high-speed, high density circuits. In addition, the source and drain structures can be raised by patterning and etching down to a silicon layer and then epitaxially depositing doped silicon or silicon which is later doped over the exposed silicon. The height of the source and drain regions is determined solely by the length and rate of deposition.


REFERENCES:
patent: 5229332 (1993-07-01), Cho
patent: 5229333 (1993-07-01), Cho
patent: 5530266 (1996-06-01), Yonehara et al.
patent: 5827769 (1998-10-01), Aminzadeh et al.
patent: 6077761 (2000-06-01), Chen et al.
Suemasu, Takashi et al. Theoretical and Measured Characteristics of Metal (CoSi2)-Insulator (CaF2) Resonant Tunneling Transistors and the Influence of Parasitic Elements. IEEE Transactions on Electron Devices. vol. 42 No. 12. Dec. 1995, pp. 2203-2210.

Affiliated with

Also associated with

Rating

Ultrascaled MIS transistors fabricated using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultrascaled MIS transistors fabricated using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultrascaled MIS transistors fabricated using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3071741