Ultra thin spacers formed laterally adjacent a gate conductor re

Details Ultra thin spacers formed laterally adjacent a gate conductor re Ultra thin spacers formed laterally adjacent a gate conductor re

1998-04-17

1999-12-07

Fahmy, Wael M.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438259, 438270, 438275, 254330, H01L 213205

Patent

active

059982888

ABSTRACT:
An integrated circuit fabrication process is provided for forming relatively thin sidewall spacers extending laterally from upper portions of opposed sidewall surfaces of a transistor gate conductor which resides partially within a trench of a semiconductor substrate. The present invention contemplates etching a trench through a masking layer and partially through a silicon-based substrate arranged underneath the masking layer. A gate dielectric is then formed upon silicon-based surfaces which border the trench. A conformal dielectric layer is deposited across the masking layer and the gate dielectric, followed by the deposition of a gate conductor material across the dielectric layer. The gate conductor material and the dielectric layer are removed from above the upper surface of the masking layer. Portions of the dielectric layer interposed between the masking layer and the gate conductor are etched to a level commensurate with the substrate surface. An LDD implant self-aligned to the lateral boundaries of the masking layer and the gate conductor sidewall surfaces is forwarded into the substrate underneath the trench. Relatively thin oxide spacer structures are then thermally grown upon the sidewall surfaces of the gate conductor. After removing the masking layer, a source/drain implant is performed. In another embodiment, the gate conductor is formed between the opposed lateral boundaries of the masking layer upon the gate dielectric. A source/drain implant is performed after removing the masking. Relatively thin dielectric spacers are formed upon the upper portions of the sidewall surfaces of the gate conductor by depositing and anisotropically etching a dielectric.

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