Ultra-thin SOI vertical bipolar transistors with an...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S587000, C257S592000, C257SE29183, C257SE29190, C257SE29198

Reexamination Certificate

active

10787002

ABSTRACT:
The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

REFERENCES:
patent: 4965872 (1990-10-01), Vasudev
patent: 5352624 (1994-10-01), Miwa et al.
patent: 5621239 (1997-04-01), Horie et al.
patent: 5627401 (1997-05-01), Yallup
patent: 7115965 (2006-10-01), Ho et al.
patent: 2004/0119136 (2004-06-01), Cai et al.
patent: 2005/0184360 (2005-08-01), Ho et al.
patent: 05243255 (1993-09-01), None

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