Ultra-thin SOI MOS transistors

Details Ultra-thin SOI MOS transistors Ultra-thin SOI MOS transistors

2005-05-24

2005-05-24

Weiss, Howard (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000

Reexamination Certificate

active

06897530

ABSTRACT:
A transistor structure includes a main gate silicon active region having a thickness of less than or equal to 30 nm; and auxiliary gate active regions located on either side of said main gate silicon active region, said auxiliary gate active regions being spaced a distance from said main gate active region of about 200 nm. A method of forming an ultra-thin SOI MOS transistor includes preparing a silicon wafer, including forming a top silicon layer having a thickness of between about 100 nm to 200 nm, thinning the top silicon layer to a thickness of between about 10 nm to 30 nm, and forming an oxide layer over the top silicon layer; forming a layer of material taken from the group of material consisting of polysilicon and silicide; forming an oxide cap on the formed layer of material, and etching the oxide cap and layer of material to form a main gate electrode and an auxiliary gate electrode on either side thereof; forming an oxide layer over the structure and etching the oxide layer to form sidewall oxide structures about the gate electrodes; depositing a layer of material taken from the group of material consisting of polysilicon, silicide and metal, etching the newly deposited layer of material, and metallizing the structure.

REFERENCES:
patent: 4824796 (1989-04-01), Chiu et al.
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5411906 (1995-05-01), Johnson et al.
patent: 5866921 (1999-02-01), Kim
patent: 08064825 (1996-03-01), None

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