Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-09-17
2004-05-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S296000
Reexamination Certificate
active
06740566
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to forming shallow trenches. In particular, the present invention relates to forming shallow trenches using an ultra-thin photoresist and a highly selective nitride etch.
BACKGROUND ART
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required. This includes the width and spacing of shallow trench isolation regions. Since there are typically numerous shallow trench isolation regions on a semiconductor wafer, the trend toward higher device densities is a notable concern.
Shallow trench isolation (STI) is increasingly popular as a means for electrically isolating devices from one another in integrated circuits. Instead of forming insulating regions around devices through local oxidation of silicon (LOCOS), trenches are etched into the substrate and then filled with insulating material (e.g., SiO
2
). Trench isolation has become a preferred form of isolation at sub-micron levels because it avoids the problems of unacceptably large encroachment of field oxides into device active regions and surface topography associated with the so-called bird's beak structure of LOCOS.
The requirement of small features (and close spacing between adjacent features) requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photomask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photomask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. However, lithography is not without limitations. Patterning features having dimensions of about 0.25 &mgr;m or less with acceptable resolution is difficult at best, and impossible in some circumstances. Patterning conductive features including shallow trench isolation regions with small dimensions is required in order to participate in the continuing trend toward higher device densities. Procedures that increase resolution, improved critical dimension control, and provide small but effective shallow trench isolation regions are therefore desired.
Lithography employing short wavelength radiation is used to improve resolution. As the wavelength decreases, however, absorbtion of radiation by the photoresist material typically increases. Consequently, the penetration depth of short wavelength radiation into photoresist materials is limited. The limited penetration depth of the shorter wavelength radiation thus requires the use of increasingly thin photoresists so that the radiation can penetrate the entire depth of the photoresist in order to effect adequate patterning thereof. However, the increasing thinness of photoresists results in a decreasingly low etch resistance. The etch protection afforded by thin photoresists is therefore limited, which in turn, limits the lithographic process.
SUMMARY OF THE INVENTION
The present invention provides methods of increasing device density by forming shallow trenches and shallow trench isolation regions with small dimensions. The present invention also provides a highly selective nitride etch that is particularly useful for forming shallow trenches and shallow trench isolation regions when employing ultra-thin photoresists. As a result, the present invention effectively addresses the concerns raised by the trend towards the miniaturization of semiconductor devices.
In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench.
In another embodiment, the present invention relates to a method of forming a shallow trench isolation region, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for a shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; etching the exposed portion of the semiconductor substrate to provide the shallow trench; and depositing an insulating filler material into the shallow trench to provide the shallow trench isolation region.
In yet another embodiment, the present invention relates to a method of forming a shallow trench isolation region, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a silicon nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the silicon nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the silicon nitride layer and to define a pattern for a shallow trench using radiation having a wavelength of about 25 nm or less; etching the exposed portion of the silicon nitride layer with an etchant having a silicon nitride:photoresist selectivity of at least about 12:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; etching the exposed portion of the semiconductor substrate to provide the shallow trench; and depositing an insulating filler material into the shallow trench to provide the shallow trench isolation region.
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Bell Scott A.
Levinson Harry J.
Lyons Christopher F.
Nguyen Khanh B.
Wang Fei
Advanced Micro Devices , Inc.
Niebling John F.
Pompey Ron
Renner , Otto, Boisselle & Sklar, LLP
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