Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-21
2002-09-17
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000, C257S347000
Reexamination Certificate
active
06452229
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor device having a thin body region and a high-K gate dielectric.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, certain materials, when used in a down-scaled device, may become electrically leaky and can cause reliability problems.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that have decreased size, enhanced performance and enhanced reliability. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET) is provided. The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source and a drain are formed from the layer of semiconductor material. A body is formed from the layer of semiconductor material and disposed between the source and the drain. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. The FET also includes a T-shaped gate having a center region formed at least in part in the recess and a pair of upper arms extending laterally from the center region, the upper arms respectively extending toward a source side of the FET and a drain side of the FET. The arms are formed over a configuring layer and the gate defines a channel in the body. The gate includes a gate electrode spaced apart from the body by a gate dielectric made from a high-K material.
According to another aspect of the invention, a method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET) is provided. The method includes providing a layer of semiconductor material, the layer of semiconductor material disposed over an insulating layer, and the insulating layer disposed over a semiconductor substrate; forming a dummy gate on the layer of semiconductor material; doping the layer of semiconductor material to form a source and a drain, and a body region between the source and the drain; forming a configuring layer over the dummy gate and extending laterally from the dummy gate over the layer of semiconductor material; patterning the configuring layer to provide a source side structural surface and a drain side structural surface; removing at least a portion of the dummy gate; etching the layer of semiconductor material to form a recess therein, the recess formed in at least the body region of the layer of semiconductor material such that a thickness of the body is less than a thickness of the source and the drain; and forming a T-shaped gate a having a center region formed at least in part in the recess and a first and a second upper arm extending laterally from the center region, the first upper arm extending toward a source side of the FET and disposed on the source side structural surface and the second upper arm extending toward a drain side of the FET and disposed on the drain side structural surface, the gate defining a channel in the body, and the gate including a gate electrode spaced apart from the body by a gate dielectric made from a high-K material.
REFERENCES:
patent: 5567966 (1996-10-01), Hwang
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6060749 (2000-05-01), Wu
patent: 6100204 (2000-08-01), Gardner et al.
patent: 6127699 (2000-10-01), Ni et al.
Advanced Micro Devices , Inc.
Ngo Ngan V.
Renner , Otto, Boisselle & Sklar, LLP
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