Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-06
2003-10-21
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S333000
Reexamination Certificate
active
06635924
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to field effect transistors (FETs) and, more particularly, to metal-oxide-semiconductor (MOS) vertical FETs or vertical MOSFETs.
2. Discussion of the Related Art
It is widely recognized that the two principal challenges to continued miniaturization of MOSFETs are electrostatic scalability and critical dimension control. The vertical replacement gate (VRG) MOSFET provides precise control of all critical dimensions without lithography, while maintaining the essential features of advanced planar MOSFETs. The partially depleted (PD) VRG MOSFETs demonstrated to date are based on a thick, lithographically defined body. See, for example, J. M. Hergenrother et al.,
IEDM Tech. Dig.,
p. 75 (1999); S-H. Oh et al.,
IEDM Tech. Dig.,
p. 65 (2000); J. M. Hergenrother et al.,
IEDM Tech. Dig.,
p. 51 (2001); J. M. Hergenrother et al.,
Proc.
2
nd
European Workshop on the Ultimate Integration of Silicon
(
ULIS
), p. 1 (2001); and J. M. Hergenrother et al., U.S. Pat. No. 6,197,641 issued on Mar. 6, 2001, all of which are incorporated herein by reference. Since short-channel effects in PD-VRG MOSFETs are controlled by the doping level of the channel (known in the art as the body), it is difficult to provide electrostatic scalability in sub-35 nm devices; i.e., in devices in which the gate length is less than about 35 nm.
Thus, there is a need in the vertical MOSFET art for better electrostatic scalability of VRG MOSFETs.
There is also a need for a VRG MOSFET that can be fully depleted (FD).
BRIEF SUMMARY OF THE INVENTION
In accordance with one aspect of our invention, a method of fabricating a VRG MOSFET includes the steps of: (a) forming a VRG multilayer stack; (b) forming a trench in the stack; (c) depositing an ultra thin, amorphous semiconductor (&agr;-semic) layer on the sidewalls of the trench and on the top of the stack (portions of the ultra thin layer on the sidewalls of the trench will ultimately form the channel or ultra thin body (UTB) of the MOSFET); (d) forming a thicker, &agr;-semic sacrificial layer on the ultra thin layer; (e) annealing the &agr;-semic layers to recrystallize them into single crystal semiconductor (x-semic) layers; (f) selectively removing the recrystallized sacrificial layer; and (g) performing additional steps to complete the VRG MOSFET. In general, the sacrificial layer should facilitate the recrystallization of the ultra thin layer into single crystal material. In addition, the etch rate of the sacrificial layer should be sufficiently higher than that of the ultra thin layer so that the sacrificial layer can be selectively removed in the presence of the ultra thin layer after recrystallization. The latter condition is illustratively satisfied by doping the sacrificial layer and by not (intentionally) doping the ultra thin layer.
In accordance with one embodiment of our invention, step (g) includes filling the trench with oxide to form a thick back oxide region In accordance with another embodiment of our invention, step (g) includes depositing a thin oxide layer (the back oxide) in the trench and then filling the remainder of the trench with a polycrystalline region (the back gate).
VRG MOSFETs fabricated in accordance with our invention are expected to be electrostatically scalable with precise dimensional control. In addition, they can be fully depleted.
In accordance with another aspect of our invention, an UTB-VRG-MOSFET includes an ultra thin x-semic layer disposed on the sidewalls of the trench. The ultra thin x-semic layer includes a pair of UTBs on opposing sidewalls adjacent the gate layer of the VRG stack, source/drain extensions above and below each UTB, and a plug that fills the remainder of the trench. In one embodiment of our invention, the plug is an oxide region (the back oxide); in another embodiment, the plug comprises a thin oxide layer (the back oxide) disposed on the ultra thin layer and a polycrystalline region (the back gate) that fills the remainder of the trench.
REFERENCES:
patent: 4914628 (1990-04-01), Nishimura
patent: 6197641 (2001-03-01), Hergenrother et al.
Ishiwara et al.,Lateral solid phase epitaxy in selectively P-doped amorphous Si films, Appl. Phys. Lett., vol. 49, No. 20, p. 1365 (Nov. 1986) (Abstract only).
Ishiwara et al.,Selective Surface Doping Method of P Atoms in Lateral Solid Phase Epitaxy. . . , Jpn. J. Appl. Phys., vol. 31, p. 1695 (Jun. 1992).
Dan et al.,Lateral solid phase epitaxy of amorphous Si films by selective surface doping method of P atoms, Appl. Phys. Lett., vol. 53, No. 26, p. 2626 (Dec. 1988).
Greene et al.,Thin Single Crystal Silicon on Oxide by Lateral Solid Phase Epitaxy of Amorphous Silicon and Silicon Germanium, Mat. Res. Soc. Symp. Proc., vol. 609, p. A9.31 (2000).
Choi et al.,Ultra-thin-Body SOI MOSFET for Deep-sub-tenth Micron Era, IEEE Electron Dev. Lett., vol. 21, No. 5, p. 254 (May 2000).
Subramanian et al.,A Bulk-Si-compatible Ultrathin SOI Technology for sub-100nm MOSFETs, Device Research Conf. Tech. Dig., p. 28 (1999).
Hergenrother et al,The Vertical Replacement-Gate . . . Gate Length, IEDM Tech. Dig., p. 75 (1999).
Oh et al,50 nm Vertical Replacement-Gate(VRG)pMOSFETs, IEDM Tech. Dig., p. 65 (2000).
Hergenrother et al,50 nm Vertical Replacement-Gate(VRG)nMOSFETs with ALD . . . Dielectrics, IEDM Tech. Dig., p. 51 (2001).
Hergenrother et al,The Vertical Replacement-Gate MOSFET, Proc. 2ndEuropean Workshop on the Ultimate Integration of Silicon (ULIS)., p. 1 (2001).
Hergenrother John Michael
Kalavade Pranav
Agere Systems Inc.
Tsai Jey
Urbano Michael J.
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