Ultra shallow junction depth transistors

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257344, 257374, 257389, 257401, 257408, 438163, 438217, 438231, H01L 31119

Patent

active

060464712

ABSTRACT:
A shallow junction MOS transistor comprising a semiconductor substrate having an upper region that includes a first and a second lightly doped region laterally displaced on either side of the channel region. The first and second lightly doped regions extend to a junction depth below the upper surface of the semiconductor substrate. A first and a second lightly doped impurity distribution are located within the first and second source/drain regions of the semiconductor substrate. The shallow junction transistor further includes a gate dielectric formed on an upper surface of the channel region of the semiconductor substrate. A conductive gate that includes a first and a second sidewall is formed on the gate dielectric. A gate insulator is formed in contact with the first and second sidewalls of the conductive gate. First and second source/drain structures are formed above the upper surface of the semiconductor substrate. The first and second source/drain structures are laterally displaced over the first and second lightly doped regions of the semiconductor substrate.

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patent: 5683924 (1997-11-01), Chan et al.
Sze, S.M., Physics of Semiconductor Devices, Second Edition, John Wiley & Sons, 1981, pp. 431-486.

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