Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-04-02
2003-06-10
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S725000, C438S733000
Reexamination Certificate
active
06576536
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to fabricating an integrated circuit with narrow lines and, more specifically, to fabricating a field effect transistor with a narrow gate width and, in addition, narrow interconnecting conductive lines.
BACKGROUND OF THE INVENTION
Field-effect transistor (FET) devices are manufactured by disposing a gate material, such as polysilicon, over a relatively thin gate insulator, such as silicon oxide on and in a semiconductor substrate. The gate material and gate insulator are patterned to form gate conductors, and impurities are deposited adjacent to and on opposite sides of the gate conductors to render the gate material more conductive and to form source/drain regions of either N-type or P-type depending on the type of impurity. If the impurity is N-type, then the resulting FET is an NMOS FET with an N-channel and, if the impurity is a P-type, then the resulting FET is a PMOS FET with a P-channel. In addition, if a device contains both an NMOS and a PMOS, the device is a CMOS.
With the increased need to fabricate more complex and higher levels of integrated circuits with faster FETs, it has become necessary to reduce the FET's threshold voltage, V
T
. One dimension of the FET which contributes to the V
T
is the effective channel length, L
eff.
, which, in turn, is influenced by the gate width. The distance between a source and a drain on opposite sides of the gate conductor is the physical channel length and may be considered equivalent to the gate width. After the deposition of the impurities, the actual distance between the source and drain is less than the physical channel length or gate width because of lateral diffusion of the impurities under the gate conductor. As the physical channel length or gate width is reduced in fabrication, the effective channel length, L
eff.
, also is reduced in length. Reducing the L
eff.
, decreases the distance between the depletion regions associated with the source and drain of the FET. By reducing the physical channel length or gate width and, in turn, the effective channel length, L
eff.
, a reduction in the threshold voltage, V
T
, of the FET can be achieved. Accordingly, the switching speed of the logic gates of an integrated circuit employing FETs with reduced L
eff
. is faster and allows the integrated circuit to quickly transition between logic states.
However, reducing the physical channel length or gate width of an FET is limited by conventional photolithographic techniques used to define the gate width of the gate conductor. Photolithography is used to pattern a photoresist, which is disposed above the gate material, such as polysilicon. An optical image is transferred to and exposes the photoresist by projecting radiation, normally deep ultraviolet light through the transparent portions of a mask plate containing the layout and dimensions of the gate conductor. Depending on whether the photoresist is positive or negative, the solubility of the exposed photoresist is either increased or decreased by a photochemical reaction. The photoresist is developed by dissolving the resist areas of higher solubility with a solvent, leaving a mask pattern on the gate material, such as polysilicon. This mask pattern protects the underlying gate material during etching of the material to define the shape and dimensions of the gate conductor and other lines in an integrated circuit.
Thus, the overlying photoresist pattern defines the lateral width of the gate conductor, which dictates the physical channel length of the FET. The minimum lateral dimension that can be achieved for a patterned photoresist is limited by the resolution of the optical system used to project the image onto the photoresist and, presently, is about 0.13 micron.
Accordingly, it would be desirable to develop an FET fabrication method in which the physical channel length or gate width of the FET can be reduced along with the effective channel length, L
eff.
, without being limited by the photolithographic system. A method which avoids the limitations of photolithographic exposure for defining the gate width of gate conductors would allow the effective channel length, L
eff.
, of the FET to be scaled down to a smaller size below 0.07 micron as well as other line widths in the integrated circuit. A method for fabricating such an FET and the FET itself would give the integrated circuit designer control over the effective channel length, L
eff.
, and allow the designer the ability to design specific operational.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of fabricating an integrated circuit with line widths, such as ultra narrow gate conductors, which permits using normal photolithographic techniques.
Another object of the present invention is to provide a method of fabricating an integrated circuit with ultra narrow gate electrodes and other line widths by a method which does not complicate the overall fabrication method of the integrated circuit.
First, a semiconductor material, such as a silicon wafer, is formed with a layer, such as polysilicon doped with an impurity and capable of functioning as a gate electrode, and with a gate insulating layer, such as an oxide, sandwiched between the silicon surface and the polysilicon. Photoresist is disposed on the polysilicon layer and exposed and developed into a pattern, including gate electrodes of minimal gate width. Now, in accordance with the present invention, the sides and the tops of the photoresist pattern, especially those defining the gate width of gate conductors are reduced in size, preferably by laser ablation, so that the photoresist pattern is reduced to a lesser dimension than that achievable by exposure to an photolithographic system alone. More specifically, a relative motion in the range of about 1000 rpm to about 5000 rpm and a relative relationship of between about 40° and about 80° is established between laser and the silicon wafer to remove photoresist on the top and sides of the photoresist pattern. Preferably, it is the silicon wafer which is spinning at about 4000 rpm in a horizontal position and it is the laser which is at angle of about 60 relative to vertical. The amount of photoresist removed is greater than about 100 Å and may be as much as 500 Å. Depending upon the specific laser, the photoresist is either evaporated or becomes more soluble in a developer or a solvent such as isopropyl alcohol/water. To assist in the decomposition of the photoresist, the laser ablation can be carried out in an oxygen-rich ambient. Next, the photoresist pattern is used as an etch mask and the gate electrode layer and insulating layer are etched to the semiconductor material surface.
REFERENCES:
patent: 4093503 (1978-06-01), Harris et al.
patent: 6174818 (2001-01-01), Tao et al.
Advanced Micro Devices , Inc.
Dang Trung
Foley & Lardner
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