Ultra low power sleep mode

Details Ultra low power sleep mode Ultra low power sleep mode

2007-12-28

2011-11-15

Auve, Glenn A (Department: 2111)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000

Reexamination Certificate

active

08060767

ABSTRACT:
An integrated circuit in accordance with one embodiment of the invention can include a plurality of storage elements that can be coupled in a first mode and a second mode. The first mode includes the plurality of storage elements being coupled to enable normal operation of the integrated circuit, and the second mode includes the plurality of storage elements being coupled together as a shift register. The integrated circuit also includes a rewritable non-volatile memory and a sleep controller that is coupled to the rewritable non-volatile memory. The sleep controller is for switching the plurality of storage elements between the first mode and the second mode. The sleep controller is for extracting data from the plurality of storage elements in the second mode and storing the data with the non-volatile memory to record the operating state of the plurality of storage elements in the first mode.

REFERENCES:
patent: 7392447 (2008-06-01), Tang et al.
patent: 2004/0088630 (2004-05-01), Arima et al.
patent: 2005/0195664 (2005-09-01), Ooishi
patent: 2008/0071972 (2008-03-01), Kimura

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