Ultra-low power multi-threshold asynchronous circuit design

Details Ultra-low power multi-threshold asynchronous circuit design Ultra-low power multi-threshold asynchronous circuit design

2011-07-12

2011-07-12

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S093000, C326S021000

Reexamination Certificate

active

07977972

ABSTRACT:
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

REFERENCES:
patent: 5305463 (1994-04-01), Fant et al.
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5652902 (1997-07-01), Fant
patent: 5656948 (1997-08-01), Sobelman et al.
patent: 5664211 (1997-09-01), Sobelman et al.
patent: 5664212 (1997-09-01), Fant et al.
patent: 5828228 (1998-10-01), Fant et al.
patent: 6031390 (2000-02-01), Fant et al.
patent: 6043674 (2000-03-01), Sobelman
patent: 6052770 (2000-04-01), Fant
patent: 6140836 (2000-10-01), Fujii et al.
patent: 6208171 (2001-03-01), Kumagai et al.
patent: 6225827 (2001-05-01), Fujii et al.
patent: 6262593 (2001-07-01), Sobelman et al.
patent: 6320418 (2001-11-01), Fujii et al.
patent: 6333640 (2001-12-01), Fant et al.
patent: 6867620 (2005-03-01), Singh et al.
patent: 6900658 (2005-05-01), Sobelman et al.
patent: 6907534 (2005-06-01), Ku
patent: 6946869 (2005-09-01), Jacobson et al.
patent: 7051306 (2006-05-01), Hoberman et al.
patent: 7053665 (2006-05-01), Singh et al.
patent: 7215155 (2007-05-01), Won
patent: 7400175 (2008-07-01), Fallah et al.
patent: 7415680 (2008-08-01), Hoberman et al.
patent: 7511535 (2009-03-01), Chakraborty et al.
patent: 7821293 (2010-10-01), Fazzi et al.
patent: 2005/0248365 (2005-11-01), Chang
patent: 2008/0133954 (2008-06-01), Fallah et al.
patent: 2008/0276105 (2008-11-01), Hoberman et al.
patent: 2009/0152948 (2009-06-01), Hoberman et al.
Al Zahrani, A. et al., “Glitch-free design for multi-threshold CMOS NCL circuits,” 2009 Great Lakes Symposium on VLSI (May 2009) 215-220.
Bailey, A.D. et al., “Multi-threshold asynchronous circuit design for ultra-low power,” J. Low Power Electronics (2008) 4(3):337-348.
Bailey, A.D. et al., “Ultra-low power delay-insensitive circuit design,” IEEE Midwest Symposium on Circuits and Systems (Aug. 20, 2008) 503-506.
Fant, K.M. et al., “NULL convention logic: A complete and consistent logic for asynchronous digital circuit synthesis,” International Conference on Application Specific Systems, Architectures and Processors (1996) 261-273.
Kao, J.T. et al., “Dual-threshold voltage techniques for low-power digital circuits,” IEEE J. Solid-State Circuits (2000) 35(7):1009-1018.
Lakshmikanthan, P. et al., “Design of ultra-low power combinational standard library cells using a novel leakage reduction methodology,” IEEE International SOC Conference (2006) 2 pages.
Mutoh, J. et al., “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits (1995) 30(8):847-854.
Smith, S.C. et al., “Delay-insensitive gate-level pipelining,” Integration, the VLSI Journal (2001) 30(2):103-131.
Smith, S.C., “Speedup of self-timed ditigal systems using early completion,” IEEE Computer Society Annual Symposium on VLSI (Apr. 2002) 107-113.
Sobelman, G.E. et al., “CMOS circuit design of threshold gales with hystereis,” IEEE International Symposium on Circuits and Systems (II) (1998) 61-65.
Smith, S.C. et al., “Optimization of NULL convention self-timed circuits,” The VLSI Journal (2004) 37(3):135-165.
Smith, S.C. et al., Designing Asynchronous Circuits Using NULL Convention Logic (NCL), Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers (Jul. 2009) vol. 4/1.

Affiliated with

Also associated with

Rating

Ultra-low power multi-threshold asynchronous circuit design does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultra-low power multi-threshold asynchronous circuit design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra-low power multi-threshold asynchronous circuit design will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2653828