Ultra-low power-delay product NNN/PPP logic devices

Details Ultra-low power-delay product NNN/PPP logic devices Ultra-low power-delay product NNN/PPP logic devices

1996-08-16

1999-10-19

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257403, 257348, 257351, H01L 2701, H01L 2976, H01L 2712, H01L 310392

Patent

active

059693851

ABSTRACT:
Transistors have source, drain and channel regions all of the same conductivity type. The channel region is very thin, not more than about 500 .ANG. and preferably about 300 .ANG. or even 100 .ANG. in thickness. A very thin oxide layer having a thickness of much less than about 100 .ANG., such as 20 .ANG. and preferably about 5 to about 10 .ANG., isolates a gate electrode from the channel region. When operated at temperatures at or below 150.degree. K, such as 77.degree. K, very low threshold voltages, well below 25 millivolts, are achieved. Gigahertz speed complementary MOS transistors, formed by adjacent NNN and PPP devices exhibit power-delay products of about 1E-16 joules operating at supply voltages on order 100 millivolts or lower, making this technology of particular interest for multi-gigahertz processing rates at very low power.

REFERENCES:
patent: 5111260 (1992-05-01), Malhi et al.
XP 002047484-"A High Performance Low Temperature 0.3 .mu.m CMOS on Simox", Shahidi, G.G. et al., Jun. 2, 1992, pp. 106-107.
Copy of Foreign Search Report.
Patent Abstracts of Japan, Y Kazuo, Sep. 17, 1990.
Tunneling Gate Oxide Approach to Ultra-High Current Device in Small Geometry MOSFETS, Momose, et al, published in IEEE, Dec., 1994.

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