Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-07-18
2004-02-17
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S062000, C326S075000, C326S077000, C326S078000
Reexamination Certificate
active
06693457
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to electrical circuits, and more particularly to an ultra high speed flip-flop.
BACKGROUND OF THE INVENTION
One major limitation of modern digital systems is the rate at which data may be transferred from one point to another. For example, in high speed computing systems where signal frequencies in excess of 100 MHZ may be found, ECL (Emitter Coupled Logic) or Current Mode Logic (CML) is often used. ECL is currently the fastest form of logic, since the active devices are arranged to operate out of saturation. ECL can provide even faster speeds by arranging that the logic signal swings are relatively small. The time required for charging and discharging various load and parasitic capacitances is quite short. ECL circuits are often preferred in high speed applications, such as telecommunication applications where increases in bit rates require increased speed of the operation of logical circuits. In these type of applications, flip-flop devices are often used to transfer data at high rates of speed.
Even though, ECL is very fast in comparison to other forms of logic, it is still provided with its limitations. Additionally, the material (e.g., Indium Phosphide (InP), Gallium Arsenide (GaA), Silicon (Si)) that the devices are constructed of has certain limitations. Presently, Gallium Arsenide (GaA) devices can operate at frequencies up to about 100 GigaHertz (GHZ), and Indium Phosphide (InP) devices can operate at frequencies up to about 300 GHZ. Gallium Arsenide (GaA) devices and Indium Phosphide (InP) are widely used in wireless and fiber optic transmission applications. As the devices begin operating at the upper range of the material, devices such as flip-flops begin to oscillate and do not operate properly. Since ECL devices are based on the use of emitter follower devices, the ECL device operate in several different logic levels that are typically separated by one or more diode drops (e.g., approximately 0.8 volt intervals). The level shifting to the different logic levels can provide additional delay to the operation of the ECL device, which can also influence the operational speed of the ECL device.
FIG. 1
illustrates a conventional ECL flip-flop
10
having a master latch portion
16
and a slave latch portion
18
. The master latch portion
16
and the slave latch portion
18
alternate between a holding state and a latching state. A differential data input (DATA (+) and DATA (−)) is provided to an open loop differential amplifier
12
that is coupled to an ECL logic component
14
. The differential data input is level shifted down from ground to a first logic level (e.g., −0.8 v to −1.6 v) through, for example, a single emitter follower (not shown). The differential data input then transitions between logic highs and lows at the first logic level. The ECL logic component
14
also receives a differential clock input signal (CLK (+) and CLK (−)). The clock input is level shifted down from ground to a third logic level (e.g., −0.2.4 v to −3.2 v) through, for example, three cascaded emitter followers (not shown). The differential clock input signal then transitions between logic highs and lows at the third logic level.
The open loop differential amplifier
12
cooperates with the ECL logic component
14
to latch data transitions of the data input through the master latch portion
16
and the slave latch portion
18
of the flip-flop
10
. The frequency of the clock signal needs to be about twice the frequency of the data rate to provide proper operation of the flip-flop
10
. As the data is transmitted through the flip-flop
10
at very high frequencies (e.g., 30-60 GHZ), the level shifting of the clock through three cascaded emitter followers creates a stability problem causing the flip-flop to oscillate and not operate properly. Therefore, limiting the operational speed of the flip-flop.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to an ultra high speed ECL flip-flop and a method of operating the same. A high frequency differential clock signal is level shifted to a first ECL logic level or voltage level range prior to being provided to the ultra high speed ECL flip-flop. The data signal is level shifted to a second or a third ECL logic level or a second or third voltage level range prior to being provided to the ultra high speed ECL flip-flop. An ECL logic component executes a clock function at the first logic level, while data is being provided to a closed loop differential amplifier at the second or third logic level. The ECL logic component and the closed loop differential amplifier cooperate to clock in data signals to a master latch portion of the ultra high speed ECL flip-flop. The master latch portion is designed to interact with the ECL logic component and the closed loop differential amplifier at the desired logic levels. The data signals are then provided to a slave latch portion of the ECL flip-flop, which latches the data signals to the output of the slave latch portion on the next clock transition.
The ECL flip-flop of the present invention can operate at significantly higher data rates than conventional flip-flop circuitry. For example, data rates from about 30 GHZ to about 60 GHZ can be achieved, since the clock input signal only experiences a single level shift. The clock signal operates at about twice the frequency of the data signal. Therefore, the level shifting the data below the clock signals provides additional bandwidth to the ECL flip-flop. Additionally, distortion is mitigated by providing a closed loop differential amplifier for receiving the data signals. The ECL flip-flop can be formed from a variety of different materials (Indium Phosphide (InP), Gallium Arsenide (GaA), Silicon (Si)), such that the outer bandwidth range of the materials is extended by the configuration of the ECL flip-flop regardless of the material type.
To the accomplishment of the foregoing and related ends, certain illustrative aspects of the invention are described herein in connection with the following description and the annexed drawings. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such aspects and their equivalents.
REFERENCES:
patent: 4692641 (1987-09-01), Highton
patent: 5068551 (1991-11-01), Bosnyak
patent: 5117124 (1992-05-01), Dicke
patent: 5220212 (1993-06-01), Sinh
patent: 5815019 (1998-09-01), Uemura et al.
patent: 5900760 (1999-05-01), Lee
Northrop Grumman Corporation
Tarolli, Sundheim Covell & Tummino L.L.P.
Tran Anh
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