Ultra high-speed DDP-SRAM cache

Details Ultra high-speed DDP-SRAM cache Ultra high-speed DDP-SRAM cache

2001-04-05

2004-06-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000, C365S156000

Reexamination Certificate

active

06751151

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache, and more particularly pertains to an ultra high-speed DDP-SRAM cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations.
2. Discussion of the Prior Art
In general, SRAM (Static Random Access Memory) memory has a higher speed than DRAM (Dynamic Random Access Memory), however it's size is much larger. A conventional SRAM cell consists of six-transistors, two nMOS transistors as transfer devices, two pull-up pMOS transistors, and two pull-down nMOS transistors. The complementary data bits which are stored in a SRAM cell are latched by a pair of back-to-back inverters. Therefore, these data do not needed to be refreshed.
On the other hand, data that is stored in a one transistor, one capacitor DRAM cell gets degraded over a period of time due to charge leakage. Therefore, for any high-speed operation, especially when the required memory density is low, SRAM memory is always the memory of choice.
As the speed of microprocessors has increased over time, the speed gap between microprocessors and SRAM cache memories has also widened. Many GHz processors have been announced recently, but the speed of the SRAM cache is still in the range of 400 MHz.
A four-T (transistor) single-port SRAM cell has been reported by NEC, titled “A 2.9 um2 Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 um High Performance CMOS Logic”, IEDM 97, p847, 1997. This single-port SRAM cell shares the transfer gates with the pull-up devices and therefore eliminates two devices per cell. This approach has significantly reduced the cell size, and surely is a very attractive design for a high-density integration. Since the pull-up and the transfer devices in NEC's cell are pMOS devices, for the unselected wordlines, the wordline voltage and all the bitline voltages are held high. The nodes are isolated since the pMOS devices are turned off. However, the leakage charge from the internal high node is constantly replenished by the off-state current flowing through the pMOS pull-up devices. There are two drawbacks with this design, (1) the cell size is not minimal, since the is a minimal ground rule specified between p-well and n-well for placing mixed pMOS and nMOS devices in a cell. (2) read/write disturb on the non-selected cell is an issue, since their bitlines are not constantly held high when the array is active.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache.
A first object of the present invention is to boost SRAM cache speed by at least 2×. A second object of the subject invention is the design of a new dual-port SRAM cell, whose size is slightly larger (less than 25% larger) than the existing single-port SRAM cache.
A further object of the subject invention is to boost the cache speed to approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations.


REFERENCES:
patent: 5541874 (1996-07-01), O'Connor
patent: 5877976 (1999-03-01), Lattimore et al.
patent: 6262912 (2001-07-01), Sywyk et al.
patent: 6608780 (2003-08-01), Shau
“An 8ns Random Cycle Embedded RAM Macro with Dual-Port Interleaved DRAM Architecture (D2RAM)”, Yasuhiro Agata et al, 2000 IEEE International Solid-State Circuits Conference, 9 pages.

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