Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-07-17
2002-03-19
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S152000, C438S197000, C257S067000, C257S069000, C257S508000
Reexamination Certificate
active
06358828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacture and, more particularly, to transistors formed on separate elevational levels and an interconnect routed between source and substrate regions on the upper level transistor to a drain of the lower level transistor to configure a high performance, high density integrated circuit.
2. Description of the Relevant Art
The structure and the various components, or features, of a metal oxide semiconductor (“MOS”) are generally well known. A MOS transistor typically comprises a substrate material onto which a patterned gate conductor is formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS (NMOS) transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS (PMOS) transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which a portion of the substrate known as a “well” exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposing junctions in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e., CMOS) are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnect to the junctions must be as small as possible. Many modern day processes employ features which have less than 1.0 &mgr;m critical dimension. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decrease. Smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the lower resolutions needed for submicron features. To some extent wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
There are many numerous other techniques used to achieve a higher density circuit, however, these techniques as well as others still must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot in all instances offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects (“SCE”) generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection (“HCI”). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric field can give rise to so called hot carriers and the injection of those carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since those carriers can become trapped and skew the turn-on voltage of the ensuing transistor.
It appears as though even the most advanced processing techniques cannot avoid in all instances the problems which arise as a result of high density fabrication. As features are shrunk and are drawn closer together across a single topological surface, the closeness of those features causes numerous problems even under the most advanced processing conditions. It therefore appears that there may be a certain limitation beyond which feature sizes cannot be reduced if those features are to reside on the single elevational level. It would therefore be desirable to derive a processing technique which can produce features on more than one level. That is, it would be beneficial that this multi-level processing technique produce both active (transistors) and passive (capacitors, resistors, etc.) in three dimensions so as to enhance the overall circuit density without incurring harmful side effects associated with feature shrinkage and closeness.
Before a three-dimensional, multi-level transistor fabrication process can be introduced, however, the process must pay careful attention to the interconnection between transistors placed on separate levels. Therefore, it is desirable to derive an interconnect scheme which can connect various features on one elevation (topological) level to features on another level. That interconnection must be as short as possible in order to minimize resistance in critical routing conductors between transistors. The desired fabrication process must therefore incorporate not only multi-level fabrication but also high performance interconnect routing as an essential part of that process.
Most logic block portions of an integrated circuit comprise transistors interconnected in various ways. For example, combinatorial logic includes, for example, NAND gates and NOR gates. Both NAND and NOR gates include series-connected transistors. More specifically, the source-drain paths of two or more transistors are connected in series between a power conductor and an output node. An example of a two-input NAND gate is shown in
FIG. 1
as reference numeral
10
.
FIG. 2
illustrates a counterpart two-input NOR gate
12
. NAND gate
10
includes a pair of n-channel transistors
14
and
15
connected in series between a ground terminal and an output Q. NOR gate
12
includes a pair of p-channel transistors
18
and
20
connected in series between a power supply and output Q.
The series-connected between two or more transistors, regardless of whether the transistors are n-channel or p-channel, presents a unique set of problems. For example, parasitic capacitance
22
a
and
22
b
is attributed to the connection between a source junction of one transistor and a drain junction of another transistor.
Parasitic capacitance
22
is the normal response of voltage placed upon a diffused junction area. Whenever the junction is coupled separate from the substrate (or “body”), capacitance occurs therebetween. More importantly, a voltage difference arises between the junction and substrate, often referred to as the “body effect”. Body effect is the term given to the modification of threshold voltage, demonstrated as a voltage difference between the source and substrate areas. In the example provided, n-channel transistor coupled at output Q will switch slower if the transistor source potential is not the same as the substrate. In most instances, the substrate will be coupled to power/ground, leaving the source of transistor
14
floating dissimilar from ground. To illustrate how the body effect changes the threshold voltage of transistor
14
, it is recognized that voltages at the input of nodes A and B may be selected such that voltage on capacitor
22
a
is charged. If the inputs are then set to a logic 1, the source terminal of transistor
14
will transition to a voltage of V
cc
minus a threshold voltage. Thus, transistor
16
will have to discharge the source node associated with capacitor
22
a
in order to turn on transistor
14
. In summary, body effect implies the fall time of transistor
14
will be slower than transistor
16
. The converse applies to the tran
Gardner Mark I.
Kadosh Daniel
Advanced Micro Devices , Inc.
Brairton Scott
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Pham Long
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