Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1998-11-13
2001-03-06
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S727000, C257S730000, C257S686000, C257S777000
Reexamination Certificate
active
06198164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a method for fabricating the same, and more particularly, to a reduced size semiconductor package and a method for fabricating the same.
2. Background of the Related Art
In semiconductor industries, integrated circuit packaging techniques have been developed ceaselessly to satisfy the demand for smaller semiconductor devices. The development of a micron integrated circuit has integrated several millions of circuit elements into a single integrated circuit on a chip and increased the importance of integrated circuit packaging, which can improve an spatial efficiency.
FIGS. 1
a
-
2
illustrate a related art semiconductor package stack T with an extended memory capacity in which Thin Small Outline Packages (TSOPs) P are stacked. The related art semiconductor package stack shown in
FIGS. 1
a
-
2
is fabricated using the following process.
First, two TSOPs P are provided, outer leads
18
of the TSOPs P are straightened, and ends of the outer leads
18
are cut. As shown in
FIG. 2
, the two TSOPs P are bonded together with polyimide adhesive
19
with their outer leads
18
aligned to each other. To connect the cut ends of the outer leads
18
on the TSOPs P, stacking rails
21
each with holes
20
are provided. The holes
20
in the stacking rails
21
and the ends of the outer leads
18
on the TSOPs P are aligned, and the outer leads
18
are inserted into the holes
20
in the rails
21
. Then, upper parts of the rail
21
are bonded to an upper surface of the top TSOP P with the adhesive
19
to prevent movement of the rail
21
as shown in
FIG. 1
a
. Solder paste is applied to upper parts of the holes
20
in the rail
21
and heated to bond the rails
21
with the outer leads
18
. The two TSOP packages are mechanically and electrically connected through the foregoing process to complete a stacked package with a twofold memory capacity as shown in
FIG. 1
b
. In the stacking type related art package shown in
FIGS. 1
a
-
2
, the TSOPs P may be stacked as many needed for a required memory capacity. For example, stacking four TSOPs of 4M DRAM capacity will make a 16M DRAM package stack.
FIG. 3
illustrates another related art stacking type package of a TAB package stacking, which is disclosed in U.S. Pat. No. 5,198,888.
However, the related art stack packages have various problems. In the related art package stacks, a stack of packages has problems in that the package stack is heavy, multiple stages of connections are exposed and the connections are weak incurring a lower mechanical reliability. Further, the lengthy signal line required for connection from chip
2
′ bonding pads to a PCB causes degradation of an electrical reliability, such as, signal delays, interferences, noises and the like in an implementation of a high speed device. The numerous bonding steps required in the fabrication process results in distortion of material and degradation of an interfacial bonding force between the chip
2
′ and encapsulation body
4
′. Defective solder paste application results from the difficulty of applying solder paste
22
to narrow package lead pitches and causes defective insulation. In addition, the requirements for a separate rail
21
fabrication process, a separate upper and lower TSOP aligning process to attach the fabricated rails to the upper surface of the package, a separate alignment process in the case of outer lead insertion into the rail holes
21
and separate process to bond upper parts of the rails
21
with the upper surface of the package causes a complex package stack fabrication process. The additional stacking after completion of individual packaging requires even more process steps, and additional equipments beyond equipments required for individual packaging, all of which increase cost and increase the length of the fabrication process.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a ultra high density integrated circuit semiconductor package and method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a semiconductor package and method for manufacturing the same that has a high device packing density.
Another object of the present invention is to provide a semiconductor package and method for manufacturing the same that has a simple fabrication process.
Another object of the present invention is to provide a semiconductor package and method for manufacturing the same with an extremely short signal transmission path.
Another object of the present invention is to provide a semiconductor package and method for manufacturing the same that without outer leads.
Another object of the present invention is to provide a semiconductor package and method for manufacturing the same with increased mechanical and electrical reliability.
Another object of the present invention is to provide a semiconductor package and method for manufacturing the same that concurrently packages individual semiconductor chips with the package.
To achieve at least these objects and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a semiconductor package includes a printed circuit board, wherein an electrical circuit is formed in the printed circuit board, a plurality of semiconductor chips substantially vertically attached to the printed circuit board, conductive members that respectively couple bonding pads on each the semiconductor chips to pads on the printed circuit board and an encapsulation body that packages the semiconductor chips and the conductive members above the printed circuit board.
To further achieve the above objects in a whole or in parts, and in accordance with the purpose of the invention, as embodied and broad described, a method for fabricating a semiconductor package includes die bonding a plurality of semiconductor chips on a printed circuit board, wherein the semiconductor chips are substantially vertically bonded to the printed circuit board, coupling bonding pads on the semiconductor chips and pads on the printed circuit board with conductive member, repeatedly performing the die bonding and the coupling steps in succession for of each of the plurality of semiconductor chips in the semiconductor package and packaging the semiconductor chips, bonding pads and conductive members with a resin.
To further achieve the above objects in a whole or in parts, and in accordance with the purpose of the invention, as embodied and broad described, a method for fabricating a semiconductor package includes applying a die bonding adhesive tape on a bottom of each of a plurality of grooves formed in an upper surface of a printed circuit board, positioning a first semiconductor chip to be wire bonded on the upper surface of the printed circuit board, wherein the first semiconductor chip is a current semiconductor chip, respectively bonding pads on the current semiconductor chip and pads on the printed circuit board with gold wires, turning over the current semiconductor chip with completed wire bonding to reverse an upper and a lower surfaces of the current semiconductor chip, positioning a successive semiconductor chip to be wire bonded on the upper surface of the printed circuit board, and wherein the successive semiconductor chip becomes the current semiconductor chip, repeating the respectively bonding pads step through the positioning a successive semiconductor chip step a prescribed number of times, standing all the wire bonded semiconductor chips vertical to the printed circuit board, applying heat and pressure to the semiconductor chips to cause bonding between the chips and a die bonding between the semicon
Cruz Lourdes
Fleshner & Kim LLP
Hardy David
Hyundai Electronics Industries Co,. Ltd.
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