Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Utility Patent
1999-11-05
2001-01-02
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S121000, C438S127000
Utility Patent
active
06168970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and apparatus for achieving ultra high density integrated circuit packages incorporating a plurality of ultra-thin encapsulated integrated circuit packages stacked and interconnected into an ultra-high density three-dimensional module.
2. Brief Description of the Related Technology.
Packaging techniques for integrated circuits have been developed in the past in an attempt to satisfy demands for miniaturization in the semiconductor industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package these circuits in space efficient, yet reliable and mass producible packages.
The introduction of highly sophisticated integrated circuit microprocessors led to the rapid development of complex personal computers and other common bus systems utilizing a variety of integrated circuit elements such as memory devices (DRAMS, VRAMS, FLASH ROMs, E PROMS, and SRAMS), programmable logic arrays (PLAs), microprocessors (CPUs), coprocessors, and other related integrated circuit elements which had to be assembled, mounted and interconnected into as compact, yet reliable packages as feasible to satisfy the industry demands for miniaturization.
Other key considerations in developing packaging for such circuits have been the cost of manufacture, the reliability of the packaged device, heat transfer, moisture penetration, standardization of mounting and interconnect methods, and the ability to test and control the quality of the packaged devices.
In the past, one area of concentration for high density packaging has been memory devices such as SRAMS and DRAMS. Prior systems typically utilized a transfer molded plastic encasement surrounding the integrated circuit and having one of a variety of pin-out or mounting and interconnect schemes. The older M-DIP (Dual-In-Line Plastic) provides a relatively flat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounting to an underlying circuit board substrate. These packages provided 100 mil spacing between leads.
A more dense package was the 100 mil SIP (Single-In-Line-Plastic) which was assembled on edge with two rows of 100-mil staggered leads extending from the bottom edge for through-hole assembly. Another popular prior art package is the PLCC (Plastic Leaded Chip Carrier) SOJ (Small Outline J-leaded) molded package with twenty surface-mount designed J-leads (length 0.67″, width 0.34″, height 0.14″). This prior art package is illustrated schematically in FIG.
1
and shown at approximate actual size in FIG.
2
.
In order to obtain more density and provide lower cost socketability (i.e. removable mounting) and to allow for after-market sale of additional memory units the SIMM (Single-In-Line Memory Module) was developed. This package is schematically illustrated in FIG.
3
. In this package typically nine one-megabyte or four-megabyte DRAMS are surface mounted into a socket which is in turn edge-mounted on a large circuit board substrate containing additional sockets or components. While this design provided some increase in density, it had the drawback of providing a module extending from one-half to nearly two inches vertically above the circuit board substrate.
Newer, higher density versions of the SIMM design with even smaller versions of the DRAM plastic package have been developed. These thinner versions of SOJ DRAMS are one-half the thickness (having a plastic packaging thickness of about 70 mils) of standard SOJ designs, and have been mounted on both sides of circuit board substrates. Even smaller TSOP packages have been developed experimentally with a plastic thickness of one millimeter and lower profile gull-wing leads for surface mounting. FIGS.
1
-
3
illustrate typical embodiments of some of these prior art packages. Based on experience with those prior art designs, for reasons of reliability related to moisture penetration and mechanical integrity, the industry has adopted a standard thickness for plastic packaging of approximately one millimeter (40 mils), or approximately 10.5 mils on each side of a 11 mil thick integrated circuit element attached to a 8 mil thick lead frame.
In contrast to such prior art systems, the packaging method of the present invention provides a reliable, cost efficient, easily manufacturable package with a plurality of ultra thin level-one package elements assembled in an integrated module or level-two package which can be mounted to a circuit board substrate directly or via an underlying socket or header.
SUMMARY OF THE INVENTION
The present invention provides new and useful embodiments of thin, yet durable and reliable, level-one packages and horizontal level-two packages.
It has been discovered that one effective way to achieve a thin and durable integrated circuit level-one package is to ensure that the casing that is molded around the die element is distributed somewhat evenly around the entire surface of the die element. The present invention provides various embodiments to achieve this result.
In one embodiment, the die element is supported in the mold, at either its bottom or top surface, by pins or supports which prevent the die element from resting flush with the bottom or top surface of the mold. Molding compound is applied on the die element surface opposite the surface supported by the supports or pins. The fluid pressure caused by the molding compound holds the die element in its proper position on the pins or supports. Since the die element is held in a horizontal position and does not rest on the top or bottom surface of the mold, the molding compound distributes somewhat evenly around all the surfaces of the integrated circuit die element. Since the molding compound distributes evenly around the integrated circuit die element, the molding compound can be applied thinner without fear that any side of the die will be inadequately covered by sufficient thickness of molding compound and, therefore, the overall integrated circuit package is thinner. The die element may be supported in the mold at both its top and bottom surface by supports. In such an embodiment, it does not matter what surface the molding compound is applied to. It is important to note that the above-described molding techniques provide thin integrated circuit packages which significantly reduce the likelihood of breaking, warping or destroying the integrity of the integrated circuit package for packages having an overall thickness of as little as twenty to twenty six mils.
In another embodiment, the integrated circuit is supported in the mold by fixed or retractable pins formed integrally with the bottom and/or upper surface or the mold. The supports may also be formed by epoxy or some other material affixed to the bottom and/or upper surfaces of the die element. When the fixed pins are used as the supports, pin holes or cavities will be left in the molded casing of the integrated circuit die element. The pin cavities may be filled in with epoxy or a secondary epoxy layer can be applied over all the surfaces of the casing. To ensure against moisture penetration and to provide enhanced stiffness to prevent warping, a metal foil layer may then be affixed to the outside surfaces of the integrated circuit package by epoxy adhesive.
It has been further discovered that lapping or polishing the lower surface of the die element before molding substantially improves the resistance to breakage during the process and, hence, permits utilization of thinner dies and an overall reduction of the package thickness without sacrificing yields. The thinnest die elements used in conventional packaging methods are typically eleven to thirteen (+/− ½ mil) mils thick. According to one aspect of the present invention, these standard die elements may be thinned by lapping or polishing the lower surfa
Collins D. M.
Denko J. Scott
George & Donaldson, L.L.P.
Picardat Kevin M.
Staktek Group L.P.
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