Ultra high density flash memory having vertically stacked device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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438212, 36518503, 36518506, H01L 29788, H01L 2976, G11C 1134

Patent

active

059733527

ABSTRACT:
An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory array includes densely packed memory cells, each cell having a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar includes source/drain and body regions and has a number of sides. A pair of vertically stacked floating gates is included on at least one of two sides of the pillar. A control gate line also passes through each memory cell. Each memory cell is associated with a control gate line so as to allow selective storage and retrieval of data on the floating gates of the cell. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F.sup.2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F.sup.2 is needed per bit of data.

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Jung, T., et al., "A 117-mm2 3.3-V Only 128-Mb Multilevel Nand Flash Memory for Mass Storage Applications", IEEE Journal of Solid-State Circuits, 31, 1575-1582, (Nov. 1996).

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