UART protocol that provides predictable delay for communication

Details UART protocol that provides predictable delay for communication UART protocol that provides predictable delay for communication

1995-03-23

1997-10-28

Bowler, Alyssa H.

39520013, 39520019, 395551, 395552, G06F 1312, G06F 1314

Patent

active

056825080

ABSTRACT:
A UART protocol which takes advantage of an SDO line space state to optimize communication between computers. A delay is provided by sending a byte of actual data followed by a dummy byte. The dummy byte is produced by placing the SDO line in the mark state, thus freeing up CPU time.

REFERENCES:
patent: 4143418 (1979-03-01), Hodge et al.
patent: 4525801 (1985-07-01), Kuwabara
patent: 4823312 (1989-04-01), Michael et al.
patent: 4984190 (1991-01-01), Katori et al.
patent: 5179706 (1993-01-01), Swanson et al.
patent: 5481675 (1996-01-01), Kapogiannis et al.
patent: 5604870 (1997-02-01), Moss et al.
patent: 5617542 (1997-04-01), Williams
Hall, "Mocroprocessors and Interfacing--Progranmming and Hardware," McGraw Hill Book Co., 1986, pp. 442-448, Dec. 1986.
Bowers et al, Machine-Cycle Extension in a Data Processor, 6 Nov. 1981.

Affiliated with

Also associated with

Rating

UART protocol that provides predictable delay for communication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with UART protocol that provides predictable delay for communication , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and UART protocol that provides predictable delay for communication will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1032240