Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-31
2001-02-20
Thai, Xuan M. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06192438
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an exchanging system, and more particularly, to an improved U-interface matching circuit and matching method capable of performing a matching function between an exchanging system and a subscriber's terminal.
2. Description of the Background Art
The conventional exchanging system employs an SCC (Serial Communication Controller) of an IMP (Integrated Multiprotocol Processor) for a U-interface matching of BRI (Basic Rate Interface) and implements a control board and hierochical three communications at the rate of 256 kbps through a SC-bus (Serial Communication-bus). Also, The exchanging system implements PCM data communication at 4.906 Mbps via an additional PCM sub-highway for the PCM matching.
As shown in
FIG. 1
, the conventional U-interface matching circuit includes a control board
10
having an SC-bus interface unit
10
-
1
and a PCM sub-highway interface unit
10
-
2
, a BRI board
20
having a plurality of BRI#
1
-BRI#n, and a DC-bus
30
and a PCM sub-highway
40
performing a U-interface matching of BRI and an additional PCM matching. The BRI boards BRI#
1
-BRI#n
20
are connected in common to the SC-bus
30
on a back plane, and a
16
-channel BRI board is mounted on the back plane.
As further shown in
FIG. 2
, the BRI boards BRI#
1
-BRI#n
20
are connected in common to 4 real lines implemented in hardware, and respective slot ID numbers are represented in 4 bits (i.e. “0011”). As a result, using the slot ID numbers from the control board
10
, the location of the BRI boards
20
mounted/demounted on/from the back plane.
The SC-bus
30
is connected to the SC-bus interface
10
-
1
of the control board
10
and at the same time to the BRI boards BRI#
1
-BRI#n, thereby being employed for signal processing and signaling so as to implement communication with the control board
10
. The SC-bus
30
includes a transmission line of 256 Kbps clock signal SCC-CLK, another transmission line of 1 ms frame synchronous signal SCC-FS, a data bus SCC-RXD for writing data on the control board
10
, and the transmission lines of data bus SCC-TXD and SC-bus seizing signal TSCASRTB.
The PCM sub-highway
40
includes a transmission line of 4.096 Mbps PCM data clock signal MCLK, an 8 KHz frame synchronous signal FSB, PCM data bus PDR for writing on the control board and PCM data bus PDX for writing on the BRI board
20
. Also, the PCM sub-highway
40
is connected to the PCM sub-highway interface unit
10
-
2
of the control board
10
and at the same time to the plurality of BRI boards BRI#
1
-BRI#n so as to employ the same for PCM data transmission/reception.
The operation of the thusly constituted conventional U-interface matching circuit will now be described with reference to the accompanying drawings.
The SC-bus
30
is connected in common to all the BRI boards
20
in the back planes. Therefore, in order to implement data transmission, the control board
10
or the respective RI boards
20
identifies the state of the SC-bus seizing signal TSCASRTB which is shared by the both thereof so as to attempt the seizing of the SC-bus
30
.
For example, in a state in which the control board
10
seizes the SC-bus
30
and transmits packet data to a third BRI board BRI#
3
. Initially, the control board
10
identifies the level of the SC-bus seizing signal TSCASRTB and checks whether the SC-bus
30
is presently employed. At this time, the SC-bus
30
is seized by the present first BRI board BRI#
1
so that the SC-bus seizing signal TSCASRTB becomes a low level. Accordingly, the control board
10
sustains the seizure of the SC-bus
30
until the SC-bus seizing signal TSCASRTB transits to a high level and waits.
When the first BRI board BRI#
1
discharges the seizure of the SC-bus
30
and the SC-bus seizing signal TSCASRTB becomes a high level, the control board
10
seizes the SC-bus
30
, and while the frame synchronous signal SCC-FS maintains a high level the slot ID numbers and the packet data are transmitted to the third BRI board BRI#
3
through the data bus SCC-RXD. In
FIG. 2
, there are provided 4 real lines implemented in hardware to provide the slot ID numbers of the respective BRI boards
20
, and the respective slot ID numbers are represented in 4 bits (i.e. “0011”).
When the control board
10
discharges the seizure of the SC-bus
30
, the BRI boards
20
seizes the SC-bus so that the packet data is transmitted to the control board
10
through the data bus SCC-TXD during a high level interval of the frame synchronous signal SCC-FS outputted from the control board
10
.
Meanwhile, in order to implement PCM matching, the conventional BRI U-interface matching circuit performs PCM data communication at 4.906 Mbps through the additional PCM sub-highway
40
. That is, the control board
10
receives/transmits PCM data DR, DX through PCM data buses PDR, PDX while the frame synchronous signal FSB at 8 KHz maintains a high level.
As discussed above, the conventional U-interface matching circuit allows the control board
10
and the respective boards
20
to seize the SC-bus
30
, receive/transmit the packet data at 256 Kbps and perform the PCM data communication at 4.906 Mbps through the additionally provided PCM sub-highway
40
.
However, the conventional U-interface matching circuit additionally requires real lines implemented in hardware to provide the slot ID numbers, as well as the SC-bus and the PCM sub-highway, thereby disadvantageously complicating the composition of the circuit in back plane design.
Further, a plurality of BRI boards in the conventional U-interface matching circuit employ the SC-bus in common, thereby increasing the possibility of data contention during the data communication.
Still further, in the conventional U-interface matching circuit, it is difficult to implement a high speed data transmission due to a low transmission speed (256 Kbps0 of the SC-bus.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming the conventional disadvantages.
Accordingly, it is an object of the present invention to provide a U-interface matching circuit capable of stably implementing the U-interface matching and PCM matching at high speed.
It is another object of the present invention to provide a U-interface matching circuit providing an SA-bus which enables a high speed data reception/transmission.
It is still another object of the present invention to provide a U-interface matching circuit and method capable f preventing a data contention by providing an independent data transmission path with regard to a plurality of BRI boards.
It is still another object of the present invention to provide a U-interface matching circuit and method capable of simplifying the circuit composition during a back plane design by integrating hardware structures for the conventional SC-bus, PCM sub-highway and slot ID numbers into one.
To achieve the above-described objects, there is provided a U-interface matching circuit according to the present invention which includes a plurality of BRI (Basic Rate Interface) boards implementing a digital subscriber's matching, a control board controlling operating modes of the plurality of BRI boards using time-divided control data, and an SA (Serial Access)-bus connected between the control board and the BRI boards and providing an independent data transmission path with regard to the plurality of BRI boards.
Further, to achieve the above-described objects, there is provided a U-interface matching method according to the present invention which includes a first step identifying mounting locations of a plurality of BRI boards, a second step reading an RX flag area of a first BRI board for data transmission and identifying whether the read RX flag is a flag representing the access complete of the first BRI board, a third step setting the first BRI mode as a write mode and transmitting the data length value and transmission data when the RX flag is a flag representing an access complet
Fleshner & Kim LLP
LG Information & Communications Ltd.
Thai Xuan M.
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