Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-05-17
2003-05-20
Etienne, Ario (Department: 2157)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C710S058000, C710S062000, C710S240000
Reexamination Certificate
active
06567878
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention relates to bus interfaces and more particularly pertains to a two wire mixed signal bi-directional bus interface for transmitting both analog and digital signals on a simplistic bus interface that requires less die area overhead and is expandable to accommodate a large number of devices of a variety in nature.
2. Background Art
Bus interfaces are commonly used in various electronic applications to allow communication between a controlling mechanism such as a microprocessor, and a plurality of peripheral parts, or devices. Prior Art
FIG. 1
shows an example of a bus interface
100
of the prior art. As shown, the bus interface includes a microprocessor
102
, a first bus
104
, a second bus
106
, and a plurality of peripheral devices
108
.
As is conventional, the microprocessor
102
communicates with the devices
108
via the first and second buses
104
and
106
using an associated bus protocol. This bus protocol comprises a set of rules for delivering and receiving information on the bus interface. Specifically, the microprocessor
102
, in accordance with the bus protocol, may “activate” or select one of the devices by identifying the same with an associated address. This is accomplished by transmitting a digital binary code to each of the devices
108
via the first bus
104
. If the binary code matches the address of one of the devices
108
, such device
108
is “activated”. Once “activated”, communication between the microprocessor
102
and the selected device
108
may ensue to the extent of accomplishing a task. For example, the device
108
may deliver the microprocessor
102
digital information by way of the second bus
106
.
Prior art bus interfaces like the one shown in Prior Art
FIG. 1
are conventionally used to pass only one type of signal, i.e. analog or digital. By passing only one type of signal, such bus interfaces are limited to working with only analog peripheral devices or digital peripheral devices.
Further, prior art bus interfaces are very complex in nature. This complexity translates into a large die area on the associated integrated circuit on which the system is built. For example, for complex protocols such as J2C and SMB, such die area would be prohibitively large. There is thus a need for a simpler bus protocol that may be more easily implemented on a smaller die area.
There is thus a need for a bus interface capable of transmitting both analog and digital signals on a simplistic bus interface that requires less die area overhead and is expandable to accommodate a large number of devices of a variety in nature.
DISCLOSURE OF THE INVENTION
The present invention comprises a bus interface including a first bus transmission medium adapted for being connected to a control signal source which generates a plurality of sequential control signals. During use, the first bus transmission medium serves to communicate the sequential control signals. Associated with the first bus transmission medium is a second bus transmission medium that is in communication with at least one peripheral device. Such device generates an output signal on the second bus transmission medium upon actuation. Tracking circuitry is connected to the device and remains in communication with the first bus transmission medium. Through this interconnection, the tracking circuitry is capable of actuating the device upon the receipt of at least one of the sequential control signals that is associated with the device and is distinguishable by a unique sequential order amongst the remaining sequential control signals.
By this design, a more simple bus protocol is provided that is not only more easily understood, but also more easily implemented on a smaller die area. Such simplicity also permits the bus interface of the present invention to be conveniently expanded to accommodate a large number of peripheral devices of a variety in nature. In addition to the foregoing benefits, the present invention also allows the communication of both analog and digital signals between a controlling mechanism and peripheral devices.
REFERENCES:
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patent: 4419758 (1983-12-01), Dorey
patent: 4810958 (1989-03-01), Takao et al.
patent: 5404460 (1995-04-01), Thomsen et al.
patent: 5524269 (1996-06-01), Hamilton et al.
patent: 5557672 (1996-09-01), Perry et al.
patent: 5715475 (1998-02-01), Munson et al.
patent: 5914957 (1999-06-01), Dean et al.
patent: 5948092 (1999-09-01), Crump
Allen Charles M.
Ashburn, Jr. Michael A.
Wettroth John M.
Etienne Ario
Maxim Integrated Products Inc.
Perkins Coie LLP
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