Two-wire interface having embedded per frame reliability...

Details Two-wire interface having embedded per frame reliability... Two-wire interface having embedded per frame reliability...

2007-10-23

2007-10-23

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10814449

ABSTRACT:
A guaranteed two-wire interface in which upon determining that an operation is to be performed on a slave component, the master component begins transmitting the frame to the slave component including an identification of the operation to be performed. The master component then transfers control of the data wire to the slave component. The slave component then transmits a remaining portion of the frame to the master component over the data wire. The frame includes reliability information such as cyclic redundancy checking data or acknowledgement data that the master component may then use to determine whether the operation was successful.

REFERENCES:
patent: 6571346 (2003-05-01), Dreps et al.
U.S. Appl. No. 10/814,483, filed Mar. 31, 2004, Dybsetter et al.

Affiliated with

Also associated with

Rating

Two-wire interface having embedded per frame reliability... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Two-wire interface having embedded per frame reliability..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-wire interface having embedded per frame reliability... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3902015